Prosecution Insights
Last updated: July 17, 2026
Application No. 19/022,713

NON-VOLATILE MEMORY DEVICE WITH VARIABLE BIT LINE CAPACITANCE AND PROGRAM METHOD THEREOF

Non-Final OA §102§103
Filed
Jan 15, 2025
Priority
Jan 26, 2024 — RE 10-2024-0012047
Examiner
HOANG, HUAN
Art Unit
Tech Center
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
93%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allowance Rate
1141 granted / 1224 resolved
+33.2% vs TC avg
Moderate +6% lift
Without
With
+5.6%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 8m
Avg Prosecution
15 currently pending
Career history
1241
Total Applications
across all art units

Statute-Specific Performance

§101
1.9%
-38.1% vs TC avg
§103
40.9%
+0.9% vs TC avg
§102
27.7%
-12.3% vs TC avg
§112
9.4%
-30.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1224 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3, 9-11, 16 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsu (CN 106796548 A). Regarding claim 1, Hsu (Fig. 3) shows a non-volatile memory device, comprising: a first memory block (BLK0) connected to bit lines (BL0-BLK); a second memory block (BLK1) connected to the bit lines and comprising string selection lines (DSG1 and SSG1); word lines (WL10-WL1n); and cell strings (350) connected to the string selection lines and the word lines; a row decoder (XDEC) configured to provide a turn-on voltage to at least one (second DSG, activates second DSG signal from the BL loading the second data to the non-volatile memory pages) of the string selection lines of the second memory block during a program operation of the first memory block; and a page buffer (322) configured to perform program or inhibit settings for the bit lines during the program operation. Regarding claim 2. Hsu (Fig. 8, t1-t3) shows the non-volatile memory device of claim 1, wherein the row decoder is further configured to provide a turn-off voltage to the word lines of the second memory block that causes memory cells of the second memory block to be set to a turn-off state during the program operation of the first memory block. Regarding claim 3, Hsu discloses the non-volatile memory device of claim 2, wherein the memory cells of the second memory block are programmed to maintain the turn-off state (the state of the memory cells of the second block) based on the turn-off voltage (Fig. 8). Regarding claim 9, Hsu discloses a method of programming a non-volatile memory device, the method comprising: setting bit lines (Fig. 3, loading the first data of the first memory block (BLK0)) of a first memory block that includes target memory cells to be programmed (The invention of one embodiment claims a method for storing information in a non-volatile memory device method and system. The method in one aspect comprises: activating the first drain select gate ("DSG") signal in response to the activated first DSG signal during a first clock cycle. loading the first data to first memory block of non-volatile memory pages from a bit line ("BL"), de-activating the first DSG signal and activates second DSG signal from the BL loading the second data to the non-volatile memory pages, and the nonvolatile memory unit second data into the second memory block of the non-volatile memory pages. the method is used for loading the data of the plurality of pages into different blocks, and then simultaneously selects a plurality of word lines are programmed. the system may include a flash memory cell array, a set of bit lines, a set of word lines, and a plurality of block decoder coupled to the plurality of blocks.); setting at least one string selection line (the second DSG signal (string select line) is activated) of a second memory block connected to the bit lines (Fig. 3, all the bit lines are connected to BLK0-BLKm) a turn-on voltage; and applying a program voltage to word lines of the target memory cells of the first memory block (the method is used for loading the data of the plurality of pages into different blocks, and then simultaneously selects a plurality of word lines are programmed). Regarding claim 10, Hsu discloses the method of claim 9, further comprising maintaining memory cells of the second memory block in a turn-off state by applying a turn-off voltage to word lines of the second memory block (Fig. 6, t2-t3). Regarding claim 11, Hsu discloses the method of claim 10, wherein the turn-off voltage is OV (Fig. 8). Regarding claim 16, Hsu discloses a non-volatile memory device, comprising: a first memory block connected to at least one bit line; and a second memory block configured to connect at least one cell string to the at least one bit line in response to a turn-on voltage applied to string selection lines during a program operation of the first memory block. Regarding claim 17, Hsu (Fig. 6) shows the non-volatile memory device of claim 16, further comprising: a row decoder configured to provide a program voltage or a pass voltage to word lines of the first memory block, and a turn-off voltage to a word line of the second memory block that causes memory cells included in the at least one cell string to maintain in a turn-off state. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 4 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu. Claims 2 and 12 differ from Hsu in reciting that the memory cells of the second blocks are programmed to an erased state. However, an erased state or a programmed state is well-known in the art to program the memory cells. It would have been obvious before the filing date of the claimed invention to use the erased state to program the memory cells in a non-volatile memory device. Allowable Subject Matter Claims 5-8, 13-15 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUAN HOANG whose telephone number is (571)272-1779. The examiner can normally be reached 7:30AM-4:00PM M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HUAN HOANG/Primary Examiner, Art Unit 2827
Read full office action

Prosecution Timeline

Jan 15, 2025
Application Filed
Jun 24, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
93%
Grant Probability
99%
With Interview (+5.6%)
1y 8m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1224 resolved cases by this examiner. Grant probability derived from career allowance rate.

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