DETAILED ACTION
General Remarks
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
5. Applicants seeking an interview with the examiner, including Microsoft Team Meeting, are encouraged to fill out the online Automated Interview Request (AIR) form
(https://www.uspto.gov/sites/default/files/documents/PTOL413A.pdf). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
6. Status of claim(s) to be treated in this office action:
a. Independent: 1, 11 and 19.
b. Pending: 1-20.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Blodgett PG PUB 20130055046 (hereinafter Blodgett), in view of Michalak PG PUB 20090027989 (hereinafter Michalak).
Regarding independent claim 1, Blodgett teaches a memory system (figures 3-6 of Blodgett, [0033]-[0037] of Blodgett), comprising:
one or more memory devices (figures 3, 4 of Blodgett); and
processing circuitry (controller indicated in [0034] of Blodgett, “…a memory controller…”) coupled with the one or more memory devices and configured to cause the memory system to:
set, to a first value (a value represented by a stored refresh marker or flag associated with memory block, the state of which is inspected at 502 in figure 5 of Blodgett) based at least in part on a memory block being scheduled for a refresh operation ([0037] of Blodgett, “…During device operation, scanning can continue on a block-by-block basis as a background task, and any necessary refreshes are queued to be completed as part of the background task or as a part of the next power cycle of the device…”, [0042] of Blodgett, “…If the number of errors exceeds the allowable threshold for read errors at 505, the block is marked for refresh at 506…”, [0046] of Blodgett, “…the block identified by the refresh block pointer is marked for refresh at 606. The data of the block is then read and copied (e.g., into a buffer memory) for reprogramming (e.g., page by page) as shown at 607, such as to update the data stored in memory with corrected and freshly programmed data…”), a refresh indication for the memory block;
initiate the refresh operation for the memory block based at least in part on setting the refresh indication to the first value (step 502-503 in figure 5 of Blodgett, [0039]-[0043] of Blodgett, Blodgett teaches determining whether a block is marked for refresh and when it is marked, copying and rewriting the block); and
monitor, during execution of the refresh operation, a value of the refresh indication, wherein the value of the refresh indication indicates whether the memory block is valid for the refresh operation ([0037] of Blodgett, [0042]-[0043] of Blodgett, [0046] of Blodgett, Blodgett teaches that the marker may remain set until copying and reprogramming are successfully completed. If power is lost or refresh is incomplete, the marker remains set so that refresh may be resumed).
But Blodgett does not expressly teach repeatedly inspecting the marker during execution.
Michalak teaches a looping refresh process in which, during execution of an overall refresh operation encompassing a plurality of independently refreshable memory units, the refresh logic repeatedly inspects the validity indicator associated wit the current refreshable memory unit before refreshing that unit. Thus the validity indicator is monitored during execution of the overall refresh operation to determine whether the corresponding memory unit remains valid for refresh.
Michalak teaches in figure 6 and [0016]-[0018] an indicator associated with each independently refreshable memory unit, and refresh logic that inspects the indicator for addressed memory unit ([0021]-[0022]), and refresh only units that contain valid data ([0027]-[0028]), and inspect the indicator after a refresh operation is indicated (figure 6, [0029]-[0030]). Therefore, Michalak teaches associating a validity indicator with an independently refreshable memory unit, inspecting the indicator when a refresh operation is requested, refreshing the unit when the indicator indicates valid data, and suppressing or skipping refresh when the indicator indicates invalid data (figure 4, [0017], [0022], [0027]-[0030]).
It would have been obvious to one of ordinary skill in the art to configure Blodgett’s refresh marker to be repeatedly inspected during execution of the block refresh operation, as taught by Michalak, while the bloc refresh is being performed page by page or portion by portion, so that refresh continues only while the block remains valid and eligible for refresh. This would avoid unnecessary copying, rewriting, power consumption, memory wear, and delay when the block has become invalid, has been reassigned, or no longer contains data requiring refresh.
Regarding claim 2, the combination of Blodgett and Michalak teaches the memory system of claim 1, wherein the processing circuitry (controller indicated in [0034] of Blodgett, “…a memory controller…”) is further configured to cause the memory system to: complete the refresh operation based at least in part on refreshing each page of a plurality of pages of the memory block and further based at least in part on the refresh indication being set to the first value, wherein the first value indicates that the memory block is valid (Blodgett teaches refreshing a memory block by reading, copying, correcting, and rewriting its stored data, see [0029]-[0030] of Blodgett, [0042] of Blodgett, [0046] of Blodgett. Michalak teaches refreshing the applicable memory unit only when its indicator remains set to indicate valid data, see [0017], [0027]-[0030] of Michalak, it would have been obvious to complete the page-by-page block refresh only while the indicator continues to show that the block is valid).
Regarding claim 3, the combination of Blodgett and Michalak teaches the memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: exit the refresh operation based at least in part on the refresh indication being set to a second value that indicates that the memory block is invalid (Michalak teaches that when the validity indicator is not set, the corresponding refresh operation is suppressed or skipped).
Regarding claim 4, the combination of Blodgett and Michalak teaches the memory system of claim 3, wherein the processing circuitry is further configured to cause the memory system to: schedule the memory block for one or more access operations different than the refresh operation based at least in part on the refresh indication being set to the second value and exiting the refresh operation (Michalak teaches that after the refresh mode concludes or when no valid refresh is performed, the memory component performs ordinary read, write, or register access operations, see 612 in figure 6, [0031]. It would have been obvious to return the block to normal access scheduling after refresh operation is skipped or terminated because the block is no longer eligible for refresh).
Regarding claim 5, the combination of Blodgett and Michalak teaches the memory system of claim 1, wherein executing the refresh operation comprises the processing circuitry configured to cause the memory system to: perform one or more iterations of the refresh operation, each iteration of the one or more iterations associated with a respective set of page lines of the memory block; and check the value of the refresh indication after each iteration of the one or more iterations of the refresh operation (Blodgett teaches in Step 604 of figure 6, and [0045]0[0047], [0052] refreshing a block incrementally by reading and checking subsets of pages, each group of pages corresponds to a respective set of page lines. Michalak teaches in [0028]-[0030] inspecting the validity indication for each current independently refreshable unit during refresh process. It would have been obvious to inspect the indicator after each page-group iteration so that the system does not continue refreshing an invalidated block, because the next inspection at step 606 in Michalak occurs after completion of the preceding IRMU refresh at step 610 and before execution of the next IRMU refresh, Michalak’s lop checks the validity indication after each completed iteration).
Regarding claim 6, the combination of Blodgett and Michalak teaches the memory system of claim 5, wherein performing each iteration of the one or more iterations comprises the processing circuitry configured to cause the memory system to: read the respective set of page lines from the memory block for refresh; and write refreshed data to the respective set of page lines in the memory block (Blodgett teaches in figure 6, [0045]-[0047] reading pages, checking or correcting data, and copying and rewriting the block).
Regarding claim 7, the combination of Blodgett and Michalak teaches the memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: move, during the execution of the refresh operation, data from the memory block to a destination memory block; set the refresh indication to a second value that indicates the memory block is invalid based at least in part on moving the data; and exit the refresh operation based at least in part on the refresh indication being set to the second value (Blodgett teaches in figure 5, [0042], [0046]-[0047] that during refresh the data of a block may be copied or relocated and rewritten. Blodgett further teaches in [0042]-[0047] clearing the block’s refresh marker after the block has been successfully reprogrammed. Clearing the marker corresponds to setting the indication to a second value indicating that the original block no longer requires or is no longer valid for the refresh operation. Michalak teaches that an invalid or cleared indication cause refresh to be suppressed ort exited).
Regarding claim 8, the combination of Blodgett and Michalak teaches the memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: write, during the execution of the refresh operation, second data to the memory block, wherein the second data overwrites first data stored in the memory block; set the refresh indication to a second value that indicates the memory block is invalid based at least in part on writing the second data to the memory block during the execution of the refresh operation; and exit the refresh operation based at least in part on the refresh indication being set to the second value (Blodgett teaches in figure 5, [0042], [0046] that during refresh the data of a block may be copied or relocated and rewritten. The reprogrammed or corrected data overwritten or replace the earlier stored data. Blodgett further in [0042]-[0046] teaches clearing the refresh marker after successful reprogramming. Michalak teaches terminating or suppressing refresh when the associated indicator is cleared or invalid).
Regarding claim 9, the combination of Blodgett and Michalak teaches the memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: determine that a valid page count associated with a quantity of pages of the memory block that include invalid data satisfies a threshold value; set the refresh indication to a second value that indicates that the memory block is invalid based at least in part on the valid page count satisfying the threshold value; and exit the refresh operation based at least in part on the refresh indication being set to the second value (Blodgett teaches in figures 5, 6 to determine whether a number of errors exceed limit, read groups of pages, and use counts of page reads or page conditions to decide whether a block require refresh. Michalak teaches maintaining valid-data indications for independently refreshable memory unit and suppressing refresh for unit without valid data. Michalak already maintains validity information at the independently refreshable unit level, while Blodgett teaches making block-refresh decisions based on numerical thresholds. A person with ordinality skill in the art would have been motivated to aggregate Michalak’s per unit validity information into a valid-page count and compare the count with a threshold, using Blodgett’s threshold-based decision technique, to avoid refreshing a block having too little remaining valid data to justify continued refresh. Counting number of valid pages rather than testing them only individually is a predictable implementation of Michalak’s validity-indicator system. Once the threshold indicates the block should not continue refreshing, Michalak teaches clearing or treating the indication as invalid and suppressing further refresh).
Regarding claim 10, the combination of Blodgett and Michalak teaches the memory system of claim 1, wherein the memory block is a virtual memory block (Michalak teaches in figures 4-5, [0024]-[0026] logical independently refreshable memory units managed by software memory managers and allocated to software tasks).
Claims 11-18 recite substantially the same operations as claims 1-8 in the form of instructions stored on a non-transitory computer-readable medium. Blodgett ([0055]-[0059]) and Michalak (figures 4-5) both teach controllers, processor, firmware or control logic implementing the disclosed refresh operations.
Claim 11 is rejected for the reason given for claim 1.
Claim 12 is rejected for the reason given for claim 2.
Claim 13 is rejected for the reason given for claim 3.
Claim 14 is rejected for the reason given for claim 4.
Claim 15 is rejected for the reason given for claim 5.
Claim 16 is rejected for the reason given for claim 6.
Claim 17 is rejected for the reason given for claim 7.
Claim 18 is rejected for the reason given for claim 8.
Claim 19 recites the method counterpart of claim 1. Claim 19 is rejected for the reason given for claim 1. Blodgett teaches marking a memory block for refresh, initiating copy-and-rewrite refresh because the block is marked, and maintaining or clearing the marker depending on completion. Michalak teaches checking the corresponding validity indicator during refresh sequence and continue or suppressing refresh depend on whether the block is valid.
Claim 20 is rejected for the reason given for claim 2. Blodgett teaches refreshing a block by processing and rewriting the pages of the block, while Michalak teaches completing refresh only for units whose validity indication remains set.
Conclusion
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824
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