DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claims 1, 4-5, and 10 are objected to because of the following informalities:
Claim 1: “an first optical delay line” in lines 23-24 should be “a first optical delay line” for further clarity.
Claim 4: “the optical switch” in line 1 should be “the N+1-level cascaded optical switch” for further clarity and continuity in the claim language.
Claim 5: “the optical switch” in line 3 should be “the N+1-level cascaded optical switch” for further clarity and continuity in the claim language.
Claim 10: “an first optical delay line” in lines 19-20 should be “a first optical delay line” for further clarity.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitations use a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are:
“the photoelectric detection module” in claims 1 and 10: ¶27, the photoelectric detection module comprises a photoelectric detector and a transimpedance amplifier.
“the sample acquisition module” in claims 1 and 10: there is no sufficient structure provided in the specification for the sample acquisition module.
“the data processing module” in claims 1 and 10: there is no sufficient structure provided in the specification for the data processing module.
“a control module” in line 5: there is no sufficient structure provided in the specification for the control module.
Because these claim limitations are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitations interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitations to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitations recite sufficient structure to perform the claimed function so as to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim limitations “the sample acquisition module,” “the data processing module,” and “a control module” in claims 1, 5, and 10 invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The disclosure is devoid of any structure that performs the function in the claim. Therefore, the claims are indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, “a reference path” in line 22 is unclear as this limitation has been mentioned previously in the same claim. Is this limitation referring to the same reference path mentioned previously or a different reference path? In light of the specification, the Examiner is interpreting this limitation to be referring to the same reference path mentioned previously. Additionally, “a sample path” in line 22 is unclear as this limitation has been mentioned previously in the same claim. Is this limitation referring to the same sample path mentioned previously or a different sample path? In light of the specification, the Examiner is interpreting this limitation to be referring to the same sample path mentioned previously. “an first optical delay line” in lines 23-24 and “a second optical delay line” in line 24 are both unclear as an optical delay line for both the reference and sample paths have already been mentioned previously in the same claim. Are these limitation referring to the same optical delay lines mentioned previously or different optical delay lines? In light of the specification, the Examiner is interpreting these limitations to be referring to the same optical delay lines mentioned previously. Additionally, “the optical delay line” in lines 32 and 34-35 respectively are unclear as a plurality of optical delay lines have been mentioned previously. To which one of the plurality of delay lines are these limitation referring? In light of the specification, the Examiner is interpreting these limitations to be referring to the optical delay lines in either the reference path or the sample path.
Claims 2-9 are rejected for their dependency on claim 1.
Regarding claim 2¸ “the optical delay line” in lines 1 and 5 respectively are unclear as a plurality of optical delay lines have been mentioned previously. To which one of the plurality of delay lines are these limitation referring? In light of the specification, the Examiner is interpreting these limitations to be referring to the optical delay lines in either the reference path or the sample path. Additionally, “a fixed optical delay amount” is unclear as an optical delay amount being fixed has been mentioned previously in claim 1, on which claim 2 is dependent. Is this limitation referring to a different delay amount mentioned previously or a different delay amount? Additionally, “wherein a length of the optical delay line on each level of the N-level cascaded optical delay line with a fixed delay amount growing exponentially” is unclear. What does this limitation mean? In light of the specification, specifically paragraph 65, the Examiner is interpreting this to mean that the length on each level grows exponentially.
Regarding claim 5, “a target delay amount” in line 4 is unclear as both a desired delay amount and a target value have been mentioned previously in claim 1, on which claim 5 is dependent. Is this limitation referring to the same desired delay amount mentioned previously, the same target value mentioned previously, or a different delay amount? In light of the specification, the Examiner is interpreting this limitation to be referring to the same desired delay amount mentioned previously. Additionally, “a relative delay amount” in line 6 is unclear as this limitation has been mentioned previously in claim 1, on which claim 5 is dependent. Is this limitation referring to the same relative delay amount mentioned previously or a different relative delay amount? In light of the specification, the Examiner is interpreting this limitation to be referring to the same relative delay amount mentioned previously.
Regarding claim 7, “a signal” in line 5 is unclear as this limitation appears to be the same as the reference signal mentioned previously. Is this limitation referring to the reference signal mentioned previously or a different signal? In light of the specification, the Examiner is interpreting this limitation to be referring to the reference signal mentioned previously. Additionally, “an echo signal” in lines 6-7 is unclear as this limitation appears to be the same as the reflection signal mentioned previously. Is this limitation referring to the reflection signal mentioned previously or a different signal? In light of the specification, the Examiner is interpreting this limitation to be referring to the reflection signal mentioned previously. Additionally, “an interference” in line 8 is unclear as this limitation has been mentioned previously in claim 1, on which claim 7 is dependent. Is this limitation referring to the interference mentioned previously or a different interference? In light of the specification, the Examiner is interpreting this limitation to be referring to the same interference mentioned previously.
Regarding claim 10, “an first optical delay line” in lines 19-20 and “a second optical delay line” in line 20 are both unclear as an optical delay line for both the reference and sample paths have already been mentioned previously in the same claim. Are these limitation referring to the same optical delay lines mentioned previously or different optical delay lines? In light of the specification, the Examiner is interpreting these limitations to be referring to the same optical delay lines mentioned previously. Additionally, “the optical delay line” in lines 28 and 30-31 respectively are unclear as a plurality of optical delay lines have been mentioned previously. To which one of the plurality of delay lines are these limitation referring? In light of the specification, the Examiner is interpreting these limitations to be referring to the optical delay lines in either the reference path or the sample path.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Allen et al. (USPGPub 20230414103 A1) in view of Swanson (USPGPub 20210356249 A1), Flanders (USPGPub 20120170046 A1), Nakamura (USPGPub 20210018312 A1), Aggarwal et al. (USPGPub 20250216632 A1), and Yu et al. (USPGPub 20250362533 A1).
Regarding claim 1, Allen teaches a time domain coherence tomography system based on a photonic integrated chip (11), comprising a light source (10), an optical chip (11), an interferometer (20), a detection module, a sample acquisition module and a data processing module (21), wherein the light source (10) is connected to the interferometer (20) by the optical chip (11), and an optical delay line (18) that is continuously adjustable (abstract, An apparatus for optical coherence tomography (OCT) scanning is described; ¶1, The invention seeks to implement an OCT scanner using photonic integrated circuit technology; see figure 2, broadband light source 10, photonic integrated circuit 11, spectrometer 20 (i.e. interferometer), processor 21, and variable delay 18; ¶15, The spectrometer can be implemented as one of an arrayed waveguide grating, AWG, a ring bus, a ring fan-out, a binary asymmetric Mach-Zehnder interferometer, AMZI, or an AMZI fan out; ¶11, A detector for analyzing and detecting the interference signal; ¶40, The spectrometer 20 analyses the spectral content of the received signal. It gives an analog or digital value of intensity for different wavelengths across the desired spectrum (which preferably encompasses the entire visible spectrum, but may extend into the IR spectrum or the UV spectrum). The spectral content is delivered to output image processor 21 to produce an image; and ¶5, The splitting of the initial signal provides a measurement signal and a reference signal, which are transmitted on a sample path and reference path, respectively); the light source (10) is configured to emit a detection light (¶39, the broadband light source 10 provides a photonic input signal to the module 11); the optical chip (11) is configured to divide the detection light into a reference path signal light and a sample path signal light, and transmit the reference path signal light by the optical delay line (18) and the sample path signal light to the interferometer (20) respectively (¶39, The module 11 has a 2×2 coupler 17 which splits the initial input signal into two signals; and ¶5, The splitting of the initial signal provides a measurement signal and a reference signal, which are transmitted on a sample path and reference path, respectively); the interferometer (20) is configured to transmit the reference path signal light to generate a reference signal, and transmitting the reference signal to the detection module; and configured to transmit the sample path signal light to a sample to be scanned to generate a reflection signal, and transmitting the reflection signal to the detection module (¶40, At the coupler 17, the two received signals interfere with each other and the resultant signal is passed to a spectrometer 20); the detection module is configured to receive the reference signal and the reflection signal, and generating an electrical signal after an interference (¶40, At the coupler 17, the two received signals interfere with each other and the resultant signal is passed to a spectrometer 20. The spectrometer 20 analyses the spectral content of the received signal. It gives an analog or digital value of intensity for different wavelengths across the desired spectrum); the sample acquisition module is configured to receive the electrical signal and transmit the electrical signal to the data processing module (21) (¶40, The spectrometer 20 analyses the spectral content of the received signal. It gives an analog or digital value of intensity for different wavelengths across the desired spectrum… The spectral content is delivered to output image processor 21); the data processing module (21) is configured to process the electrical signal to obtain an image of the sample to be scanned (¶40, The spectral content is delivered to output image processor 21 to produce an image, which can be displayed on a display of the image processor 21 or can be analysed by that processor or can be stored and sent for remote viewing); the optical chip (11) comprises an optical input port (14), a light splitter (17), a reference path, a sample path, a first output port, and a second output port; the reference path, having an first optical delay line which is continuously adjustable, and the sample path being arranged respectively and symmetrically (see figure 2, optical port 14 (i.e. optical input port) having coupler 17 (i.e. splitter), two unlabeled output paths that include both a reference and sample path, the paths being arranged respectively and symmetrically, two output ports via waveguides 15 and 23); after having been input, the detection light is divided into the reference path signal light and the sample path signal light by the light splitter (17), while the reference path signal light is output by the first output port, and the sample path signal light is output by the second output port (see figure 2; and ¶5, The splitting of the initial signal provides a measurement signal and a reference signal, which are transmitted on a sample path and reference path, respectively); the optical delay line (18) is of a spiral structure; and/or the reference path of the optical chip further has a link (50) arranged, the link (50) is formed by an N+1-level cascaded optical switch (511-515) and an N-level cascaded optical delay line (52-55), while an optical delay amount of each level of the optical delay line (52-55) is fixed but different; wherein N is a positive integer (see figure 5; and ¶64, a binary delay 50 with several integrated tunable switches 511, 512, 513, 514, and 515 where ‘L’ stands for a pre-defined unit delay. The upper ‘rail’ on the binary delay 50 have fibre optic, free space, or integrated photonic delay lines 52, 53, 54, and 55 of lengths L, 2L, 4L, and 8L respectively between each tunable switch 511, 512, 513, 514, and 515 that may have an order of magnitude of 2.sup.n which correspond to delays of 2.sup.n unit delays, where n is a positive integer); the reference path signal light passes through the first optical delay line (18) and passes through the link (50), and being output by the first output port (see figure 2; and ¶64, The combination of the two rails results in a reprogrammable path length, wherein a desired delay to the reference signal can be implemented); the sample path signal light being output by the second output port directly (see figure 2); after determining a delay matching most with a desired delay amount, through the first optical delay line and the sample path at a front end, a relative delay amount of the two paths is accurately locked to a target value (¶65, In operation, the multiple of L is calculated for a desired delay, and the tunable switches are configured so that the signal travels a path length matching the desired delay). However, Allen fails to explicitly teach wherein both a reference path and a sample path of the optical chip have an optical delay line arranged respectively; wherein the photoelectric detection module comprises a photoelectric detector and a transimpedance amplifier; wherein the input and output ports are formed by respective edge couplers; and the optical chip comprises a silicon substrate, a buried oxide layer, a silicon nitride waveguide layer, and a metal electrode.
However, Swanson teaches wherein both a reference path and a sample path of the optical chip have an optical delay line arranged respectively (¶21, This type of variable delay may be placed in the sample arm, the reference arm, or both the sample arm and the reference arm).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Allen to incorporate the teachings of Swanson to include a variable delay line in both the reference and sample paths because [t]his VDL provides the variable delay between the two arms of the interferometer that is necessary to match their path lengths as required by the system (Swanson, ¶21). However, the combination fails to explicitly teach wherein the photoelectric detection module comprises a photoelectric detector and a transimpedance amplifier; wherein the input and output ports are formed by respective edge couplers; and the optical chip comprises a silicon substrate, a buried oxide layer, a silicon nitride waveguide layer, and a metal electrode.
However, Flanders teaches wherein the detection module comprises a detector (348) and a transimpedance amplifier (350) (¶39, The two detectors 348 along with the transimpedance amplifier 350 are integrated together on a common optical bench 110 . This bench 110 is further installed within an optoelectronic package 200).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Allen and Swanson to incorporate the teachings of Flanders to further include a detector with a transimpedance amplifier because [t]he integration of the detectors 348 on a common optical bench 110 along with the transimpedance amplifier 350 improves the electronic performance of the system (Flanders, ¶40). However, the combination fails to explicitly teach wherein the detector is a photoelectric detector; wherein the input and output ports are formed by respective edge couplers; and the optical chip comprises a silicon substrate, a buried oxide layer, a silicon nitride waveguide layer, and a metal electrode.
However, Nakamura teaches wherein the detector is a photoelectric detector (abstract, The photoelectric conversion measuring means obtains interference light intensity measurement values by causing object light scattered from the object to be measured and the reference light to interfere with each other and to be guided to a light receiver).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Allen, Swanson, and Flanders to incorporate the teachings of Nakamura to have the detectors be photoelectric detectors as these are very common in the art. However, the combination fails to explicitly teach wherein the input and output ports are formed by respective edge couplers; and the optical chip comprises a silicon substrate, a buried oxide layer, a silicon nitride waveguide layer, and a metal electrode.
However, Aggarwal teaches wherein the input and output ports are formed by respective edge couplers (¶105, the photonic ports, e.g., input and output photonic ports, for the active photonic component can be optically coupled to a fiber array unit (FAU)… the FAU can also be coupled to the photonic port through an edge coupler).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Allen, Swanson, Flanders, and Nakamura to incorporate the teachings of Aggarwal to further include an edge coupler in order to efficiently couple light from an external source into a photonic chip and vice versa. However, the combination fails to explicitly teach wherein the optical chip comprises a silicon substrate, a buried oxide layer, a silicon nitride waveguide layer, and a metal electrode.
However, Yu teaches wherein the optical chip comprises a silicon substrate, a buried oxide layer, a silicon nitride waveguide layer, and a metal electrode (¶29, one or more silicon photonic circuits 150 are provided on a layer of buried oxide (BOX) 203 disposed over a manufacturing substrate 201. Manufacturing substrate 201 can be a silicon wafer; ¶22, Silicon photonic circuit 150 can further include one or more optical structures, such as first and second waveguides 115a and 115b… First and second waveguides 115a and 115b can include elongated sections of a suitable material, such as silicon or silicon nitride; and ¶23, Silicon photonic circuit 150 may further include at least one electrode… one or more electrodes 117a-117d include stacked layers of conducting (such as metal), semi-conducting, and insulating materials).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Allen, Swanson, Flanders, Nakamura, and Aggarwal to incorporate the teachings of Yu to have the photonic chip be a silicon on insulator device as these devices are common in photonics.
Regarding claim 2, Allen as modified by Swanson, Flanders, Nakamura, Aggarwal, and Yu teaches the system according to claim 1, wherein a length of the optical delay line on each level of the N-level cascaded optical delay line with a fixed delay amount growing exponentially, while a delay amount of a next-level optical delay line is greater than a delay amount of a previous-level optical delay line; and/or the fixed delay amount of a first-level optical delay line is less than or equal to a maximum delay amount of the optical delay line (Allen, ¶64, a binary delay 50 with several integrated tunable switches 511, 512, 513, 514, and 515 where ‘L’ stands for a pre-defined unit delay. The upper ‘rail’ on the binary delay 50 have fibre optic, free space, or integrated photonic delay lines 52, 53, 54, and 55 of lengths L, 2L, 4L, and 8L respectively between each tunable switch 511, 512, 513, 514, and 515 that may have an order of magnitude of 2.sup.n which correspond to delays of 2.sup.n unit delays, where n is a positive integer).
Regarding claim 3, Allen as modified by Swanson, Flanders, Aggarwal, and Yu teaches the first output port and the second output port of the optical chip (Allen, see figure 2, optical port 14 (i.e. optical input port) and two unlabeled output paths that include both a reference and sample path, the paths being arranged respectively and symmetrically, two output ports via waveguides 15 and 23). However, the combination fails to explicitly teach wherein the output ports of the optical chip are coupled through a bi-channel optical fiber array, and the sample path signal light is collimated by an optical fiber collimator.
However, Nakamura teaches wherein the output ports of the optical chip are coupled through a bi-channel optical fiber array, and the sample path signal light is collimated by an optical fiber collimator (¶36, connection lines between blocks in the drawings include both bidirectional and unidirectional. The one-way arrow schematically shows the flow of a main signal (data), and it does not exclude bidirectionality; and ¶44, The object light passes through a fiber collimator 105).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Allen, Swanson, Flanders, Aggarwal, and Yu to incorporate the teachings of Nakamura to further include bi-channel optical fibers as they allow data to be transmitted and received in both directions simultaneously over a single fiber, thereby decreasing the hardware needs. Additionally, it would have been obvious to further include a collimator in the sample path in order to prevent the scattering of measurement light in all directions, thereby allowing for a strong signal to be reflected from the sample and transmitted to the detector.
Regarding claim 4, Allen as modified by Swanson, Flanders, Nakamura, Aggarwal, and Yu teaches the system according to claim 1, wherein the optical switch (Allen 511-515) is a 2x2 type adiabatic directional coupler or a multimode interferometer (Allen, ¶70, The tunable switches 511, 512, 513, 514, and 515 are like individual two-way switches. Each MZI allows switching (selection, via the phase shift) to the bottom or top output of the MZI; and ¶73, There may be a need to switch from one to many different outputs/delay lengths (a multiplexer). Multiplexers can be many cascaded MZIs that ‘fan-out’ to many optical paths or more complex N×N MZI structures (rather than a simple 2×2). Each of these (2×2 MZIs and N×N MZIs) will be controlled by a phase shift as described above).
Regarding claim 5, Allen as modified by Swanson, Flanders, Nakamura, Aggarwal, and Yu teaches the system according to claim 1, wherein further comprising a control module (Allen 20), configured to adjust a delay amount of the first optical delay line and a delay amount of the second optical delay line (Allen, ¶39, The variable delay 18 is controlled by an internal control module 22 via a control path 29; and Swanson, ¶21, This type of variable delay may be placed in the sample arm, the reference arm, or both the sample arm and the reference arm); and configured to control the optical switch (Allen 511-515 | Swanson 302) on each level to adjust a total optical delay amount; after determining a target delay amount and selecting a plurality of optical switches (Allen 511-515 | Swanson 302) to generate a delay most matching the target delay amount, together with the delay amount of the first optical delay line and the delay amount of the second optical delay line, a relative delay amount between two paths is locked accurately to the target delay amount (Swanson, ¶61, Switches 302 can connect to a controller 308 that can direct the switch state of each switch to select the desired path with its associated desired delay).
Regarding claim 8, Allen as modified by Swanson, Flanders, Nakamura, Aggarwal, and Yu teaches the system according to claim 1, wherein further comprising a scanning element (Allen 12), and the scanning element (Allen 12) comprises a two-dimensional rotating mirror (Allen, ¶34, The imaging optics 12 comprise a scanning unit containing two independent mirrors rotatable about perpendicular axes); the scanning element (Allen 12) is configured to guide the sample path signal light emitted by the interferometer to the sample to be scanned by the two-dimensional rotating mirror, so as to generate a plurality of echo signals at a plurality of different positions of the sample to be scanned, and completing extracting an information on a specific depth level of the sample to be scanned (Allen, see ¶¶35-36; and see ¶¶2-8 regarding scanning for depth).
Regarding claim 9, Allen as modified by Swanson, Flanders, Nakamura, Aggarwal, and Yu teaches the system according to claim 1, wherein the light source (Allen 10) is a low coherence broadband light source; and/or the interferometer is a Michelson interferometer (Allen, ¶2, Optical coherence tomography (OCT) scanning is an imaging technique using low-coherent light to capture two- and three-dimensional images from within a media; and ¶15, The means for providing the first signal is preferably a broadband light source).
Regarding claim 10, Allen teaches a time domain coherence tomography method based on a photonic integrated chip (11) (abstract, An apparatus for optical coherence tomography (OCT) scanning is described; and ¶1, The invention seeks to implement an OCT scanner using photonic integrated circuit technology), wherein comprising: emitting a detection light by a light source (10) (¶39, the broadband light source 10 provides a photonic input signal to the module 11); dividing a detection light into a reference path signal light and a sample path signal light by an optical chip (11), and transmitting the reference path signal light, by an optical delay line (18) which is continuously adjustable, and the sample path signal light to an interferometer (20) (¶5, The splitting of the initial signal provides a measurement signal and a reference signal, which are transmitted on a sample path and reference path, respectively; and see figure 2, broadband light source 10, photonic integrated circuit 11, spectrometer 20 (i.e. interferometer), processor 21, and variable delay 18); transmitting the reference path signal light to generate a reference signal by the interferometer (20), then transmitting the reference signal to a detection module; and transmitting the sample path signal light to a sample to be scanned to generate a reflection signal, then transmitting the reflection signal to the detection module (¶40, At the coupler 17, the two received signals interfere with each other and the resultant signal is passed to a spectrometer 20; and see ¶39 for further details); receiving the reference signal and the reflection signal by the detection module, and generating an electrical signal after an interference (¶40, At the coupler 17, the two received signals interfere with each other and the resultant signal is passed to a spectrometer 20. The spectrometer 20 analyses the spectral content of the received signal. It gives an analog or digital value of intensity for different wavelengths across the desired spectrum); receiving the electrical signal by a sample acquisition module and transmitting the electrical signal to a data processing module (21) (¶40, The spectrometer 20 analyses the spectral content of the received signal. It gives an analog or digital value of intensity for different wavelengths across the desired spectrum… The spectral content is delivered to output image processor 21); processing the electrical signal to obtain an image of the sample to be scanned by the data processing module (21) (¶40, The spectral content is delivered to output image processor 21 to produce an image, which can be displayed on a display of the image processor 21 or can be analysed by that processor or can be stored and sent for remote viewing); the optical chip (11) comprises an optical input port (14), a light splitter (17), a reference path, a sample path, a first output port, and a second output port; the reference path, having an first optical delay line (18) which is continuously adjustable, and the sample path being arranged respectively and symmetrically (see figure 2, optical port 14 (i.e. optical input port) having coupler 17 (i.e. splitter), two unlabeled output paths that include both a reference and sample path, the paths being arranged respectively and symmetrically, two output ports via waveguides 15 and 23); after having been input, the detection light is divided into the reference path signal light and the sample path signal light by the light splitter (17), while the first output port outputs the reference path signal light, and the second output port outputs the sample path signal light (see figure 2; and ¶5, The splitting of the initial signal provides a measurement signal and a reference signal, which are transmitted on a sample path and reference path, respectively); the optical delay line (18) is of a spiral structure; and/or the reference path of the optical chip (11) further has a link (50) arranged, the link (50) is formed by an N+1-level cascaded optical switch (511-515) and an N-level cascaded optical delay line (52-55), while an optical delay amount of each level of the optical delay line is fixed but different; wherein N is a positive integer (see figure 5; and ¶64, a binary delay 50 with several integrated tunable switches 511, 512, 513, 514, and 515 where ‘L’ stands for a pre-defined unit delay. The upper ‘rail’ on the binary delay 50 have fibre optic, free space, or integrated photonic delay lines 52, 53, 54, and 55 of lengths L, 2L, 4L, and 8L respectively between each tunable switch 511, 512, 513, 514, and 515 that may have an order of magnitude of 2.sup.n which correspond to delays of 2.sup.n unit delays, where n is a positive integer); the reference path signal light passes through the first optical delay line (18) and passes through the link (50), and being output by the first output port (see figure 2; and ¶64, The combination of the two rails results in a reprogrammable path length, wherein a desired delay to the reference signal can be implemented); the sample path signal light being output by the second output port directly (see figure 2); after determining a delay matching most with a desired delay amount, through the first optical delay line and the sample path at a front end, a relative delay amount of the two paths is accurately locked to a target value (¶65, In operation, the multiple of L is calculated for a desired delay, and the tunable switches are configured so that the signal travels a path length matching the desired delay). However, Allen fails to explicitly teach wherein both a reference path and a sample path of the optical chip have an optical delay line arranged respectively; wherein the photoelectric detection module comprises a photoelectric detector and a transimpedance amplifier; wherein the input and output ports are formed by respective edge couplers; and the optical chip comprises a silicon substrate, a buried oxide layer, a silicon nitride waveguide layer, and a metal electrode.
However, Swanson teaches wherein both a reference path and a sample path of the optical chip have an optical delay line arranged respectively (¶21, This type of variable delay may be placed in the sample arm, the reference arm, or both the sample arm and the reference arm).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Allen to incorporate the teachings of Swanson to include a variable delay line in both the reference and sample paths because [t]his VDL provides the variable delay between the two arms of the interferometer that is necessary to match their path lengths as required by the system (Swanson, ¶21). However, the combination fails to explicitly teach wherein the photoelectric detection module comprises a photoelectric detector and a transimpedance amplifier; wherein the input and output ports are formed by respective edge couplers; and the optical chip comprises a silicon substrate, a buried oxide layer, a silicon nitride waveguide layer, and a metal electrode.
However, Flanders teaches wherein the detection module comprises a detector (348) and a transimpedance amplifier (350) (¶39, The two detectors 348 along with the transimpedance amplifier 350 are integrated together on a common optical bench 110 . This bench 110 is further installed within an optoelectronic package 200).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Allen and Swanson to incorporate the teachings of Flanders to further include a detector with a transimpedance amplifier because [t]he integration of the detectors 348 on a common optical bench 110 along with the transimpedance amplifier 350 improves the electronic performance of the system (Flanders, ¶40). However, the combination fails to explicitly teach wherein the detector is a photoelectric detector; wherein the input and output ports are formed by respective edge couplers; and the optical chip comprises a silicon substrate, a buried oxide layer, a silicon nitride waveguide layer, and a metal electrode.
However, Nakamura teaches wherein the detector is a photoelectric detector (abstract, The photoelectric conversion measuring means obtains interference light intensity measurement values by causing object light scattered from the object to be measured and the reference light to interfere with each other and to be guided to a light receiver).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Allen, Swanson, and Flanders to incorporate the teachings of Nakamura to have the detectors be photoelectric detectors as these are very common in the art. However, the combination fails to explicitly teach wherein the input and output ports are formed by respective edge couplers; and the optical chip comprises a silicon substrate, a buried oxide layer, a silicon nitride waveguide layer, and a metal electrode.
However, Aggarwal teaches wherein the input and output ports are formed by respective edge couplers (¶105, the photonic ports, e.g., input and output photonic ports, for the active photonic component can be optically coupled to a fiber array unit (FAU)… the FAU can also be coupled to the photonic port through an edge coupler).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Allen, Swanson, Flanders, and Nakamura to incorporate the teachings of Aggarwal to further include an edge coupler in order to efficiently couple light from an external source into a photonic chip and vice versa. However, the combination fails to explicitly teach wherein the optical chip comprises a silicon substrate, a buried oxide layer, a silicon nitride waveguide layer, and a metal electrode.
However, Yu teaches wherein the optical chip comprises a silicon substrate, a buried oxide layer, a silicon nitride waveguide layer, and a metal electrode (¶29, one or more silicon photonic circuits 150 are provided on a layer of buried oxide (BOX) 203 disposed over a manufacturing substrate 201. Manufacturing substrate 201 can be a silicon wafer; ¶22, Silicon photonic circuit 150 can further include one or more optical structures, such as first and second waveguides 115a and 115b… First and second waveguides 115a and 115b can include elongated sections of a suitable material, such as silicon or silicon nitride; and ¶23, Silicon photonic circuit 150 may further include at least one electrode… one or more electrodes 117a-117d include stacked layers of conducting (such as metal), semi-conducting, and insulating materials).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Allen, Swanson, Flanders, Nakamura, and Aggarwal to incorporate the teachings of Yu to have the photonic chip be a silicon on insulator device as these devices are common in photonics.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Allen et al. (USPGPub 20230414103 A1) in view of Swanson (USPGPub 20210356249 A1), Flanders (USPGPub 20120170046 A1), Nakamura (USPGPub 20210018312 A1), Aggarwal et al. (USPGPub 20250216632 A1), and Yu et al. (USPGPub 20250362533 A1) as applied to claim 1 above, and further in view of Hu et al. (USPGPub 20210307603 A1).
Regarding claim 6, Allen as modified by Swanson, Flanders, Nakamura, Aggarwal, and Yu teaches wherein the light source (Allen 10) is coupled to the optical chip (Allen 11) (Allen, see figure 2). However, the combination fails to explicitly teach wherein the light source is coupled to the optical chip through an optical fiber in a coupling manner of a coupler or a lens.
However, Hu teaches wherein the light source is coupled to the optical chip through an optical fiber in a coupling manner of a coupler or a lens (¶39, This OCT engine 100 is coupled to a broadband light source 110, such as a superluminescent diode (SLD), that emits a broadband beam 111 into an optical fiber 112 that is coupled to a waveguide in the substrate 102).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Allen, Swanson, Flanders, Nakamura, Aggarwal, and Yu to incorporate the teachings of Hu to provide the emitted light from the light source into the photonics chip using an optical fiber to prevent any signal loss.
Allowable Subject Matter
Claim 7 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Regarding claim 7, the prior art of record individually or combined fails to teach the system according to claim 1 as claimed, wherein the photoelectric detection module is arranged between the interferometer and the sample acquisition module; the photoelectric detection module comprises a photoelectric detector and a transimpedance amplifier; the photoelectric detector is configured to receive a signal of the reference path signal light having been transmitted through the interferometer as the reference signal, and receive an echo signal generated by the sample to be scanned as the reflection signal; and more specifically in combination with configured to generate a current signal after an interference between the reference signal and the reflection signal, and transmit the current signal to the transimpedance amplifier; the transimpedance amplifier is configured to generate a voltage signal correspondingly according to the current signal, and transmit the voltage signal to the sample acquisition module.
Conclusion
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/ERIN R GARBER/Examiner, Art Unit 2878
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