Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Response to Arguments
Claims 1-8 are pending.
Applicant’s arguments with respect to amended claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1-8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8 of U.S. Patent No. 12259624 B2 (hereinafter ‘624 patent) in view of Enda et al., US 20100141849 A1 (hereinafter “Enda”).
Claim 1 of ‘624 patent
Claim 1 of pending application
A semiconductor device comprising a pixel portion, the pixel portion comprising:
A liquid crystal display device comprising:
a scan line extending in a first direction and comprising a first region having an opening and
a second region being adjacent to the first region of the scan line,
a full width of the first region of the scan line being larger than a full width of the second region of the scan line in a top view;
a scan line extending in a first direction and comprising a first region comprising an opening and
a second region being adjacent to the first region of the scan line;
a first wiring comprising a first part extending in parallel to the first direction and a second part adjacent to the first part, a full width of the first part of the first wiring being smaller than a full width of the second part of the first wiring in the top view;
a capacitor wiring comprising a first part extending in parallel to the first direction and a second part adjacent to the first part, a full width of the first part of the capacitor wiring being smaller than a full width of the second part of the capacitor wiring in the top view;
a semiconductor film overlapping with the first region of the scan line;
wherein the semiconductor film comprises amorphous silicon,
an amorphous silicon film overlapping with the first region of the scan line;
a signal line comprising a first part extending in parallel to a second direction intersecting with the first direction, a second part extending in parallel to the first direction and overlapping with the opening of the scan line, and a third part being over and in contact with the semiconductor film;
a signal line comprising a first part extending in parallel to a second direction intersecting with the first direction, a second part extending in parallel to the first direction and overlapping with the opening of the scan line, and a third part being over and in contact with the amorphous silicon film;
a conductive layer having a first region being over and in contact with the semiconductor film and
a second region overlapping with the first part and the second part of the first wiring;
and
a conductive layer including a first region facing the third part of the signal line over the amorphous silicon film and
a second region overlapping with the first part and the second part of the capacitor wiring;
and
a pixel electrode over the first wiring and the conductive layer,
the pixel electrode being in contact with the second region of the conductive layer,
a pixel electrode electrically connected to the second region of the conductive layers; and
wherein the first wiring comprises same materials of the scan line, and
wherein the capacitor wiring comprises a same material as the scan line, and
wherein the conductive layer comprises same materials of the signal line.
wherein the conductive layer comprises a same material as the signal line
Claim 2 of ‘624 patent
Claim 2 of pending application
The semiconductor device according to claim 1,
wherein each of the scan line and the first wiring comprises a stacked layer using metal materials selected from molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, and nickel.
The liquid crystal display device according to claim 1,
wherein each of the scan line and the capacitor wiring comprises a stacked layer using metal materials selected from molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, and nickel.
Claim 3 of ‘624 patent
Claim 3 of pending application
The semiconductor device according to claim 1,
wherein each of the signal line and the conductive layer comprises a stacked layer using metal materials selected from molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, and nickel.
The liquid crystal display device according to claim 1,
wherein each of the signal line and the conductive layer comprises a stacked layer using metal materials selected from molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, and nickel.
Claim 4 of ‘624 patent
Claim 4 of pending application
The semiconductor device according to claim 1,
wherein the scan line and the first wiring are provided over and in contact with a surface of a substrate.
The liquid crystal display device according to claim 1,
wherein the scan line and the first wiring are provided over and in contact with a surface of a substrate.
Claim 5 of ‘624 patent
Claim 5 of pending application
A semiconductor device comprising a pixel portion, the pixel portion comprising:
A liquid crystal display device comprising:
a scan line extending in a first direction and comprising a first region having an opening and
a second region being adjacent to the first region of the scan line,
a full width of the first region of the scan line being larger than a full width of the second region of the scan line in a top view;
a scan line extending in a first direction and comprising a first region comprising an opening and
a second region being adjacent to the first region of the scan line;
a first wiring comprising a first part extending in parallel to the first direction and a second part adjacent to the first part, a full width of the first part of the first wiring being smaller than a full width of the second part of the first wiring in the top view;
a capacitor wiring comprising a first part extending in parallel to the first direction and a second part adjacent to the first part, a full width of the first part of the capacitor wiring being smaller than a full width of the second part of the capacitor wiring in the top view;
a semiconductor film overlapping with the first region of the scan line;
wherein the semiconductor film comprises amorphous silicon,
an amorphous silicon film overlapping with the first region of the scan line;
a signal line comprising a first part extending in parallel to a second direction intersecting with the first direction, a second part extending in parallel to the first direction and overlapping with the opening of the scan line, and a third part being over and in contact with the semiconductor film;
a signal line comprising a first part extending in parallel to a second direction intersecting with the first direction, a second part extending in parallel to the first direction and overlapping with the opening of the scan line, and a third part being over and in contact with the amorphous silicon film;
a conductive layer having a first region being over and in contact with the semiconductor film and
a second region extending in parallel to the first direction and overlapping with the first part and the second part of the first wiring;
and
a conductive layer including a first region facing the third part of the signal line over the amorphous silicon film and
a second region extending in parallel to the first direction and overlapping with the first part and the second part of the capacitor wiring;
and
a pixel electrode over the first wiring and the conductive layer,
the pixel electrode being in contact with the second region of the conductive layer,
a pixel electrode electrically connected to the second region of the conductive layers; and
wherein the first wiring comprises same materials of the scan line, and
wherein the capacitor wiring comprises a same material as the scan line, and
wherein the conductive layer comprises same materials of the signal line.
wherein the conductive layer comprises a same material as the signal line
Claim 6 of ‘624 patent
Claim 6 of pending application
The semiconductor device according to claim 5,
wherein each of the scan line and the first wiring comprises a stacked layer using metal materials selected from molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, and nickel.
The liquid crystal display device according to claim 5,
wherein each of the scan line and the capacitor wiring comprises a stacked layer using metal materials selected from molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, and nickel..
Claim 7 of ‘624 patent
Claim 7 of pending application
The semiconductor device according to claim 5,
wherein each of the signal line and the conductive layer comprises a stacked layer using metal materials selected from molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, and nickel.
The liquid crystal display device according to claim 5,
wherein each of the signal line and the conductive layer comprises a stacked layer using metal materials selected from molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, and nickel.
Claim 8 of ‘624 patent
Claim 8 of pending application
The semiconductor device according to claim 5,
wherein the scan line and the first wiring are provided over and in contact with a surface of a substrate.
The liquid crystal display device according to claim 5,
wherein the scan line and the first wiring are provided over and in contact with a surface of a substrate.
Comparing the reference patent with pending application, the subject matter of pending claims is covered by the scope of claims of the reference patent, except for the following:
the semiconductor device in ‘624 patent is a liquid crystal display device in pending application,
the first wiring in ‘624 patent is capacitor wiring in pending application,
the conductor layer including a first region facing the claimed third region of semiconductor film
In same field of endeavor of a semiconductor device (a display device with semiconductor transistor in pixel), Enda discloses (relevant sections highlighted in bolded below) a semiconductor device being a liquid crystal display device (paragraphs 40-42, 123, liquid crystal display panel) comprising:
a scan line extending in a first direction and comprising a first region having an opening and a second region being adjacent to the first region of the scan line, a full width of the first region of the scan line being larger than a full width of the second region of the scan line in a top view (fig. 20, scan line 16, paragraph 119, 165, see annotated figures below);
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a first wiring capacitor wiring extending in parallel to the first direction, the first wiring being a capacitor wiring (fig. 20, paragraphs 119, 158, capacitor lines 18a / 18b, see annotated figure below);
a semiconductor film overlapping with the first region of the scan line (fig. 20, fig. 36, paragraphs 128, 160, 161, semiconductor film 24 corresponding to transistors 12a / 12b, see annotated figure below);
the signal line comprising a first part extending in parallel to a second direction intersecting with the first direction a second part extending in parallel to the first direction and overlapping with the opening of the scan line, and a third part being over and in contact with the semiconductor film (fig. 20, paragraph 119, data signal line 15, see annotated figure below);
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a conductive layer (fig. 20, paragraphs 128, 158, 161, drain electrode 8a / 8b and drain draw line 27a / b extended from 8a / 8b) including a first region facing the third part of the signal line over the semiconductor film and a second region overlapping with the first wiring (see annotated figure 20, 36 below); and
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a pixel electrode (fig. 20, paragraphs 119, 159, pixel electrode 17a / 17b) over the first wiring and the conductive layer, the pixel electrode electrically connected with the second region of the conductive layer (see annotated fig. 20 below, paragraph 158, “A first contact hole 11 a connecting the first drain drawing line 27 a and the first pixel electrode 17 a is provided on the end portion of the first drain drawing line 27 a, and a second contact hole 11 b connecting the second drain drawing line 27 b and the second pixel electrode 17 b is provided on the end portion of the second drain drawing line 27 b),
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Both Enda and the ‘624 patent disclose similar display device with active matrix pixels and opening in scanning line having similar construction but with minor structural modification, it would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the known structure of providing a matrix of pixels with signal lines, scanning lines, transistors with semiconductor film and conductive layer to be controlled by the signal lines and scan lines to drive pixel electrodes, such as disclosed by Enda, into the ‘624 patent, to constitute wherein the semiconductor device is a liquid crystal display device, the first wiring is capacitor wiring, and the conductor layer include a first region facing the third region of the semiconductor film, such is incorporation of known elements into a known device to yield predictable result, the result would have been predictable and intended function of allowing display device to display content based on image signal would have been the same.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEIJIE SHEN whose telephone number is (571)272-5522. The examiner can normally be reached Monday - Friday 10AM - 6PM.
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/PEIJIE SHEN/Examiner, Art Unit 2622
/PATRICK N EDOUARD/Supervisory Patent Examiner, Art Unit 2622