DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Application filed January 16, 2025.
Claims 1-20 are pending. Claims 1, 10 and 16 are independent.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on January 16, 2025. This IDS has been considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-8 and 10-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-5, 8-13 and 15-18 of U.S. Patent No. U.S. 12,211,556. Although the claims at issue are not identical, they are not patentably distinct from each other because: application claims 1-8 and 10-20 are anticipated by 12,211,556 claims 1-5, 8-13 and 15-18.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-5 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (U.S. 2014/0063940; hereinafter “Chen”).
Regarding independent claim 1, Chen discloses a method comprising:
receiving a program command that involves a program operation having a first pass in which a first voltage is applied to a plurality of memory cells and a second pass in which a second voltage is applied to the plurality of memory cells (Figs. 7B-7C, see also page 6, par. 0083-0084);
performing the first pass of the program operation using a first sensing time (see page 13, par. 0178); and
performing the second pass of the program operation using a second sensing time (see page 13, par. 0178), wherein the first sensing time is shorter than the second sensing time (see page 13, par. 0178).
Regarding claim 3, Chen discloses performing the program operation from a source region of the plurality of memory cells (Fig. 4: lower terminal of cells) to a drain region of the plurality of memory cells (Fig. 4: upper terminal of cells).
Regarding claim 4, Chen discloses performing the program operation from a drain region of the plurality of memory cells (Fig. 4: upper terminal of cells) to a source region of the plurality of memory cells (Fig. 4: lower terminal of cells).
Regarding claim 5, Chen discloses altering a program voltage associated with the first pass of the program operation to a second program voltage when performing the second pass of the program operation (“a series of programming voltage pulses (with increasing magnitudes), see page 5, par. 0068).
Regarding claim 9, Chen discloses wherein the program command involves a program operation having at least three passes (Figs. 8A-8C).
Claims 10-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang (U.S. 2020/0066363).
Regarding independent claim 10, Yang discloses an apparatus (Fig. 2), comprising:
an array comprising memory blocks (Fig. 2); and
a controller coupled to the array and configured to (Fig. 2: 268), in response to receiving a program command that involves a programming operation involving a plurality of programming passes (see page 7, par. 0082):
control performance of a first programming pass using a first sensing time based on a first type of the first programming pass (a sensing time if a programming condition has been satisfied, see page 7, par. 0082); and
control performance of a second programming pass using a second sensing time based on a second type of the second programming pass (another sensing time if a programming condition has not been satisfied, see page 7, par. 0082).
Regarding claim 11, Yang discloses wherein the controller is further configured to determine a plurality of corresponding sensing times for each of the plurality of programming passes (see pages 6-7, par. 0076-0081).
Regarding claim 12, Yang discloses wherein the plurality of corresponding sensing times are each different sensing times that correspond to each of the plurality of programming passes (see pages 6-7, par. 0076-0081).
Regarding claim 13, Yang discloses wherein the first type and the second type correspond to a sequence of a corresponding programming pass (“Figs. 9A-D represents the distribution of a set of memory cell after a series of program loops are delivered,” see pages 6-7, par. 0076).
Regarding claim 14, Yang discloses wherein the controller is further configured to increase a programming voltage associated with the first programming pass for the threshold voltage states associated with memory cells of the memory blocks that are greater than a threshold voltage (see pages 5-6, par. 0068).
Regarding claim 15, Yang discloses wherein the controller is further configured to increase a voltage step for the threshold voltage states associated the memory cells that are greater than the threshold voltage (see pages 5-8, par. 0068), wherein the first sensing time is decreased in response to the controller increasing the voltage step (see page 7, par. 0082).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U.S. 2014/0063940; hereinafter “Chen”) in view of Sharon (U.S. 2013/0163330).
Regarding claim 2, Chen discloses the limitations with respect to claim 1.
However, Chen is silent with respect to wherein the first pass of the program operation is a coarse program operation and the second pass of the program operation is a fine program operation.
Similar to Chen, Sharon teaches a series of program and verify pulses during program operation (see page 1, par. 0021) using two different sensing time (see page 2, par. 0057).
Furthermore, Sharon teaches wherein the first pass of the program operation is a coarse program operation (see page 18, par. 0214) and the second pass of the program operation is a fine program operation (see page 18, par. 0214).
Since Sharon and Chen are from the same field of endeavor, the teachings described by Sharon would have been recognized in the pertinent art of Chen.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Sharon with the teachings of Chen for the purpose of allow simultaneous multi-threshold sensing, see Sharon’s page 2, par. 0057.
Regarding claim 8, Chen discloses the limitations with respect to claim 1.
However, Chen is silent with respect to wherein the first sensing time is at least twenty-five percent less than the second sensing time.
Similar to Chen, Sharon teaches a series of program and verify pulses during program operation (see page 1, par. 0021) using two different sensing time (see page 2, par. 0057).
Furthermore, Sharon teaches wherein the first sensing time is at least twenty-five percent less than the second sensing time (a long FSENSE ranging from 600ns to 1600ns and a short FSENSE is 500ns; 666.67ns is within the range of 600ns to 1600ns and to obtain 500ns, 25% of 666.67 is 166.67 and 666.67 – 166.67 is equal 500ns, see page 3, par. 0061).
Since Sharon and Chen are from the same field of endeavor, the teachings described by Sharon would have been recognized in the pertinent art of Chen.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Sharon with the teachings of Chen for the purpose of allow simultaneous multi-threshold sensing, see Sharon’s page 2, par. 0057.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U.S. 2014/0063940; hereinafter “Chen”) in view of Yang (U.S. 2020/0066363).
Regarding claim 6, Sharon discloses the limitations with respect to claim 1.
However, Sharon is silent with respect to increasing a program voltage associated with the first pass of the program operation for threshold voltage states associated with the plurality of memory cells that have greater than a particular threshold voltage associated therewith.
Similar to Sharon, Yang teaches a series of program loops including an alteration circuit configured to alter the sensing time of subsequent program loop (see Abstract).
Yang teaches increasing a program voltage associated with the first pass of the program operation for threshold voltage states associated with the plurality of memory cells that have greater than a particular threshold voltage associated therewith (see pages 5-6, par. 0068).
Since Yang and Chen are from the same field of endeavor, the teachings described by Yang would have been recognized in the pertinent art of Chen.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Yang with the teachings of Chen for the purpose of achieve a desired result of a determined threshold voltage of the memory cell, see Yang’s page 5, par. 0062.
Regarding claim 7, Chen in combination with Yang teaches the limitations with respect to claim 6.
Furthermore, Yang teaches decreasing the first sensing time for the threshold voltage states associated with the plurality of memory cells that have greater than the particular threshold voltage associated therewith (Figs. 11A-11C, see also pages 7-8, par. 0085).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825
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