DETAILED ACTION
General Remarks
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
5. Applicants seeking an interview with the examiner, including Microsoft Team Meeting, are encouraged to fill out the online Automated Interview Request (AIR) form
(https://www.uspto.gov/sites/default/files/documents/PTOL413A.pdf). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
6. Status of claim(s) to be treated in this office action:
a. Independent: 2, 12 and 17.
b. Pending: 2-21.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 9 recites, “the at least one access line includes and additional access line”, it has grammar issue. For the purpose of continuing examination, the limitation has been interpreted as “the at least one access line includes additional access line”.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12232311. Although the claims at issue are not identical, they are not patentably distinct from each other, many claims in present application appear to take the parent claims and replace “channel region” with “semiconductor region” and “data line” with “conductive region”, while retaining essentially the same structural relationships.
Claim 2 of instant application [Wingdings font/0xE0]claim 9 or 1 of parent 12232311
Claim 3 of instant application [Wingdings font/0xE0]claim 10of parent 12232311
Claim 4 of instant application [Wingdings font/0xE0]claim 9 of parent 12232311
Claim 5 of instant application [Wingdings font/0xE0]claim 9 or 11 of parent 12232311
Claim 6 of instant application [Wingdings font/0xE0]claim 9 of parent 12232311
Claim 7 of instant application [Wingdings font/0xE0]claim 9-11 of parent 12232311
Claim 8 of instant application [Wingdings font/0xE0]claim 6 or 12 of parent 12232311
Claim 9 of instant application [Wingdings font/0xE0]claim 9-11 of parent 12232311
Claim 10 of instant application [Wingdings font/0xE0]claim 2 of parent 12232311
Claim 11 of instant application [Wingdings font/0xE0]claim 13 of parent 12232311
Claim 12 of instant application [Wingdings font/0xE0]claim 1 of parent 12232311
Claim 13 of instant application [Wingdings font/0xE0]claim 13 of parent 12232311
Claim 14 of instant application [Wingdings font/0xE0]claim 6 of parent 12232311
Claim 15 of instant application [Wingdings font/0xE0]claim 6 of parent 12232311
Claim 16 of instant application [Wingdings font/0xE0]claim 2+13 of parent 12232311
Claim 17 of instant application [Wingdings font/0xE0]claim 14 of parent 12232311
Claim 18 of instant application [Wingdings font/0xE0]claim 15 of parent 12232311
Claim 19 of instant application [Wingdings font/0xE0]claim 16 of parent 12232311
Claim 20 of instant application [Wingdings font/0xE0]claim 17 of parent 12232311
Claim 21 of instant application [Wingdings font/0xE0]claim 18 of parent 12232311
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 2-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shukuri US Patent 5357464 (hereinafter Shukuri).
Regarding independent claim 2, Shukuri teaches an apparatus (title) comprising:
a memory cell (figures 1, 7, 8) including:
a first transistor (RM in figures 1, 7, 8) including a charge storage structure (“floating gate” in paragraph (9), “…self-amplifying memory cell in FIG. 7 has a reading transistor (RM) having a floating gate which acts as a charge storage node…”) and a first semiconductor region (channel/source-drain structure of RM in figures 1, 7, 8), the charge storage structure (“floating gate” in paragraph (9), “…self-amplifying memory cell in FIG. 7 has a reading transistor (RM) having a floating gate which acts as a charge storage node…”, e.g., 97 in figure 23) including a first side (the lower end/face of 97 toward 92 in figure 23) and a second side (the upper end/face of 97 toward 102 in figure 23) opposite from the first side, the first semiconductor region (channel/source-drain structure of RM in figures 1, 7, 8, e.g., channel region 101, drain region 102, source region 92 in figure 23) including a portion (lower portion of 101 lies adjacent first side of charge-storage node 97 and is separated by gate insulating film 99, see figure 23) located at the first side (the lower end/face of 97 toward 92/91 in figure 23) of the charge storage structure and separated from the first side of the charge storage structure by a dielectric material (99 in figure 23); and
a second transistor (WM in figures 1, 7, 8) including a second semiconductor region (source-drain structure of WM in figures 1, 7, 8, e.g., 15 in figure 11) coupled to the charge storage structure;
a conductive region (a conductive source/drain connection associated with RM, including the conductive connection to source/drain region 92/102 in figure 23) coupled to the portion (lower portion of 101 lies adjacent first side of charge-storage node 97 and is separated by gate insulating film 99, see figure 23) of first semiconductor region; and
at least one access line (WW, RW in figure 7) associated with the memory cell.
Regarding claim 3, Shukuri teaches the apparatus of claim 2, further comprising an additional conductive region (DL in figure 1, bit line 106) coupled to the second semiconductor region (source-drain structure of WM in figures 1, 7, 8).
Regarding claim 4, Shukuri teaches the apparatus of claim 2, wherein the charge storage structure (“floating gate” in paragraph (9), “…self-amplifying memory cell in FIG. 7 has a reading transistor (RM) having a floating gate which acts as a charge storage node…”, e.g., 97 in figure 23) includes a third side (lateral/vertical side wall of 97 extending between first side and second side in figure 23) between the first side and the second side, and the first semiconductor region (channel/source-drain structure of RM in figures 1, 7, 8) includes an additional portion (lateral/vertical portion of channel 101 extending along the third side of 97) located at the third side of the charge storage structure and separated from the third side of the charge storage structure.
Regarding claim 5, Shukuri teaches the apparatus of claim 4, further comprising an additional conductive region (source/drain conductive connection associated with the additional semiconductor /source-drain portion of RM in figure 23 and corresponding conductive paths shown in figures 1, 7, 8, interconnect pad 103/bit line 106 through drain region 102) coupled to the additional portion of the first semiconductor region.
Regarding claim 6, Shukuri teaches the apparatus of claim 4, wherein the additional portion of the first semiconductor region is a first additional portion (lateral/vertical portion of channel 101 extending along the third side of 97) of the first semiconductor region, and the first semiconductor region includes a second additional portion (upper portion of channel 101 adjacent drain region 102, at the upper/second side of charge storage node 97 in figure 23) located at the second side (the upper end/face of 97 toward 102 in figure 23) of the charge storage structure.
Regarding claim 7, Shukuri teaches the apparatus of claim 6, further comprising an additional conductive region (e.g., Pad 103 in figure 23) coupled to the second additional portion (upper portion of channel 101 adjacent drain region 102, at the upper/second side of charge storage node 97 in figure 23) of the first semiconductor region.
Claims 12-15, 17-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JEON PG PUB 20130256774 (hereinafter JEON).
Regarding independent claim 12, JEON teaches an apparatus comprising:
a memory cell (figure 1, figure 6A-6E, figure 12, figure 5) including: a first transistor (RTr in figure 1, 5 or figure 10, [0082], “…read transistor RTr…”) including a charge storage structure (MN/MNG in figure 1, 5 or 10, [0082], “…memory node gate MNG may be disposed between the control gate RCG and a channel region of the read transistor RTr…”) and a first semiconductor region (read-channel region RCH in figure 6B) separated from the charge storage structure; and
a second transistor (WTr in figure 1 and 10, [0082], “…write transistor WTr…”) including a second semiconductor region (body/channel region WB in figure 6C) coupled to the charge storage structure, wherein the charge storage structure (MN in figure 1 or 6, 10) is between the second semiconductor region (body/channel region WB in figure 6C) and the first semiconductor region (read-channel region RCH in figure 6C);
a first conductive region (read-side conductive/source-drain connection coupled to RCH, including the common source/source interconnection SI, see [0086] and figures 6A-6D) coupled to the first semiconductor region (read-channel region RCH in figure 6B);
a second conductive region (the other RTr source/drain conductive connection, or RBL, see [0084], [0086]) coupled to one of the first semiconductor region and the second semiconductor region; and
at least one access line (WL1/WL2 in figure 1) separated from the first semiconductor region (read-channel region RCH in figure 6B) and the second semiconductor region (body/channel region WB in figure 6C).
Regarding claim 13, JEON teaches the apparatus of claim 12, wherein the first conductive region (read-side conductive/source-drain connection coupled to RCH, including the common source/source interconnection SI, see [0086] and figures 6A-6D) includes a length in a first direction, and the at least one access line includes a length in a second direction (Jeon in figure 6A shows the source/data conductive structures extending along one array direction and the word line conductive structure extending transversely along another direction).
Regarding claim 14, JEON teaches the apparatus of claim 12, wherein the at least one access line (RCG/WL1 in figure 1, figure 6A-6E) includes an access line adjacent the first semiconductor region (read-channel region RCH in figure 6B).
Regarding claim 15, JEON teaches the apparatus of claim 12, wherein the at least one access line (WG1/WG2/WL1/WL2, is adjacent body/channel region WB of WTr in figure 5, 6A-6E) includes an access line adjacent the second semiconductor region.
Regarding independent claim 17, JEON teaches an apparatus comprising:
a memory cell (figure 1, figure 6C, figure 12) including: a first transistor (RTr in figure 1 or figure 10, [0082], “…read transistor RTr…”) including a charge storage structure (MN/MNG in figure 1 or 10, [0082], “…memory node gate MNG may be disposed between the control gate RCG and a channel region of the read transistor RTr…”) including a first side and a second side opposite from the first side, and a first semiconductor region (read-channel region RCH in figure 6B) separated from the charge storage structure; and
a second transistor (WTr in figure 1 and 10, [0082], “…write transistor WTr…”) including a second semiconductor region (body/channel region WB in figure 6C) located at the first side of the charge storage structure and coupled to the charge storage structure (Jeon shows in figure 6C WB lies at the first side of the storage structure while RCH lies at the opposite side);
a first conductive region (read-side conductive/source-drain connection coupled to RCH, including the common source/source interconnection, see [0086] and figures 6A-6D) located at the second side of the charge storage structure and separated from the charge storage structure, the first conductive region coupled to the first semiconductor region and including a length in a first direction;
a second conductive region (the other RTr source/drain conductive connection, e.g., RBL/RBLC, see [0084], [0086]) coupled to the first semiconductor region; and
at least one additional conductive region (RCG/WL1 in figure 6A is adjacent RCH and extending in the cross-word line direction, or common first gate electrode 111/WL1 structure) adjacent the first semiconductor region and including length in a second direction.
Regarding claim 18, JEON teaches the apparatus of claim 17, wherein the first conductive region is coupled to a ground connection (Jeon teaches that one source/drain terminal of RTr may be connected to a common source region tied to ground, [0086], “…second source/drain terminal of the read transistor RTr may be connected to a common source region to which a reference voltage (e.g., a ground voltage) is applied…”).
Regarding claim 19, JEON teaches the apparatus of claim 17, further comprising an additional conductive region (WBL coupled to WTr in figure 1) coupled to the second semiconductor region.
Regarding claim 20, JEON teaches the apparatus of claim 17, wherein the at least one additional conductive region includes a portion spanning across part of the first semiconductor region (WL1/RCG extends across and control a portion of RTr channel region, first gate electrode 111/WL1/RCG extends across a portion of the read channel region RCH, see figure 6A-6C, [0120]).
Regarding claim 21, JEON teaches the apparatus of claim 17, wherein the at least one additional conductive region (a plurality of gate/word line conductive regions, common first gate electrode 111/WL1 structure) includes: a first additional conductive region (RCG/WL1 spanning/overlying the RTr first semiconductor/channel region) spanning across part of the first semiconductor region; and a second additional conductive region (WG/WL2 or WBL-related conductive structure, adjacent /coupled with body/channel region WB of WTr) adjacent the second semiconductor region.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Shukuri US Patent 5357464 (hereinafter Shukuri), in view of JEON PG PUB 20130256774 (hereinafter JEON).
Regarding claim 8, Shukuri teaches the apparatus of claim 2 including a first semiconductor region associated with reading transistor RM and word line/access line for controlling the memory cell. But Shukuri does not teach wherein the at least one access line includes an access line adjacent a first side of the first semiconductor region and separated from the first side of the semiconductor region.
However, Jeon teaches a semiconductor transistor structure in which a gate/word line electrode is disposed adjacent a respective portion/side of a semiconductor body and is separated from the semiconductor body by a gate dielectric.
It would have been obvious to one of ordinary skill in the art before the effective filing date to configure the access-line/gate structure of Shukuri according to the gate arrangement taught by Jeon, thereby positioning the access line adjacent to and electrically insulated from a side of the semiconductor region, because such insulated gate positioning is a known transistor-control arrangement permitting the gate to electrically control the semiconductor channel while remaining electrically isolated.
Regarding claim 9, the combination of Shukuri and Jeon teaches the apparatus of claim 8, wherein the at least one access line includes and additional access line adjacent a second side of the first semiconductor region and separated from the second side of the first semiconductor region (Jeon teaches a semiconductor body controlled by a plurality of separately identifiable gate electrodes (e.g., 111, 112, 113 in figure 6A-6B), wherein the respective gate electrodes are disposed adjacent different portion/sides of the semiconductor body and are separated from the semiconductor body by gate dielectric material. Therefore, it would have been obvious to provide Shukuri’s first semiconductor region with an additional insulated access-line/gate structure adjacent another side of the semiconductor region, as taught by Jeon, to provide additional electrostatic control over the semiconductor region and predicable transistor operation).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Shukuri US Patent 5357464 (hereinafter Shukuri), in view of Sharma PG PUB 20200091156 (hereinafter Shama).
Regarding claim 10, Shukuri teaches the apparatus of claim 2, wherein the first semiconductor region and the second semiconductor region associated with the reading transistor RM and writing transistor WM, respectively.
But Shukuri does not teach the first semiconductor region and the second semiconductor region include different materials.
However, Shama teaches in [0048] use of a semiconductor oxide material, including indium gallium zinc oxide, as channel material.
Shukuri and Sharma are analogous art because they address the same field of endeavor: memory storage apparatuses control circuit designs and control methods therefor. At the time of the effective filing, it would have been obvious to one of ordinary skill in the art, having the teachings of Shukuri and Sharma before him, with reasonable expectation of success, to adopt indium gallium zinc oxide as channel material for one of the semiconductor region of Shukuri, while retaining the silicon/polycrystalline-silicon material for the other semiconductor region, as a known alternative semiconductor channel implementation, thereby resulting in the first region and second regions including different materials.
Regarding claim 11, the combination of Shukuri and Shama teaches the apparatus of claim 2, wherein the second semiconductor region includes a semiconducting oxide material ([0048] of Shama, “…Active thin-film layers (e.g., indium gallium zinc oxide (IGZO)), forming a channel layer of each of an access TFT and a gain TFT…”, it would have been obvious to substitute the known semiconducting-oxide channel material of Shama for the semiconductor channel material of Shukuri’s second transistor to employ a known semiconductor material for the same transistor channel function, with predictable transistor operation).
Claims 16 is rejected under 35 U.S.C. 103 as being unpatentable over JEON PG PUB 20130256774 (hereinafter JEON), in view of Shukuri US Patent 5357464 (hereinafter Shukuri), and Sharma PG PUB 20200091156 (hereinafter Shama).
Regarding claim 16, JEON teaches the apparatus of claim 12, but does not teach wherein the first semiconductor region includes a polysilicon material, and the second semiconductor region includes a semiconducting oxide material.
Shukuri teaches use of polycrystalline silicon in its transistor, for example, Shukuri describes formation of semiconductor/channel material using polycrystalline silicon.
However, Shama teaches in [0048] use of a semiconductor oxide material, including indium gallium zinc oxide, as channel material.
At the time of the effective filing, it would have been obvious to one of ordinary skill in the art, having the teachings of Jeon, Shukuri and Sharma before him, with reasonable expectation of success, to select channel material from a limited choices, such that to adopt indium gallium zinc oxide as channel material for one of the semiconductor region of Jeon, while adopt the silicon/polycrystalline-silicon material for the other semiconductor region of Jeon, each performing its known semiconductor channel function.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOCHUN L CHEN whose telephone number is (571)272-0941. The examiner can normally be reached on M-F: 9AM-5:00PM.
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824
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