Prosecution Insights
Last updated: October 02, 2026
Application No. 19/024,056

MAGNETIC MEMORY DEVICE

Non-Final OA §103
Filed
Jan 16, 2025
Priority
Jun 13, 2024 — RE 10-2024-0076948
Examiner
BASHAR, MOHAMMED A
Art Unit
2824
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
95%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allowance Rate
641 granted / 674 resolved
+27.1% vs TC avg
Minimal +3% lift
Without
With
+3.3%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
22 currently pending
Career history
696
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
69.9%
+29.9% vs TC avg
§102
5.9%
-34.1% vs TC avg
§112
4.8%
-35.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 674 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Information Disclosure Statement Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered. Foreign Priority Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been placed in the file of record. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US Pub # 2017/0104029). Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. Regarding independent claim 1, Li et al. teach a magnetic memory device comprising: a memory cell connected to a bit-line and a word-line and including a first magnetic tunnel junction element (see Fig. 2-3, 4 and paragraph 0028-0038, 0036-0055, 0057-0063, 0065-0069, 0081-0086, 220 MTJ element, BL is bitline, WL is word-line); and a second magnetic tunnel junction element and a metal word-line on the word-line, and electrically connected to the word-line (see Fig. 2-3, 4 and paragraph 0028-0038, 0036-0055, 0057-0063, 0065-0069, 0081-0086, wordline coupled to dummy structure area). Even though Li et al. teach wordline both for normal cell and dummy cell but silent exclusively about metal word-line. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Li et al. where gate of transistor dummy cell coupled to wordline through metal line which would be called metal wordline in order to effectively control and improve the device with reduced electromagnetic interference (see paragraph 0004). Regarding claim 2, Li et al. teach, wherein a width of the second magnetic tunnel junction element is different from a width of the first magnetic tunnel junction element in an elongate direction of the word-line and the metal word-line (see Fig. 2-3, 4 and paragraph 0028-0038, 0036-0055, 0057-0063, 0065-0069). Regarding claim 3, Li et al. teach, wherein a width of the second magnetic tunnel junction element is greater than a width of the first magnetic tunnel junction element in an elongate direction of the word-line and the metal word-line (see Fig. 2-3, 4 and paragraph 0028-0038, 0036-0055, 0057-0063, 0065-0066). Regarding claim 4, Li et al. teach, wherein the word-line and the metal word-line are spaced apart in a first direction, and wherein a height of the second magnetic tunnel junction element is different from a height of the first magnetic tunnel junction element in the first direction (see Fig. 2-3, 4 and paragraph 0028-0038, 0036-0055, 0057-0063, 0065-0068). Regarding claim 5, Li et al. teach, wherein the word-line and the metal word-line are spaced apart in a first direction, and wherein a height of the second magnetic tunnel junction element is greater than a height of the first magnetic tunnel junction element in the first direction (see Fig. 2-3, 4 and paragraph 0028-0038, 0036-0055, 0057-0063). Regarding claim 6, Li et al. teach, further comprising a third magnetic tunnel junction element on the word-line and connected in parallel with the second magnetic tunnel junction element, and wherein the third magnetic tunnel junction element is electrically connected to the metal word-line and the word-line (see Fig. 2-3, 4 and paragraph 0028-0038, 0036-0055, 0057-0063, 0065-0069). Regarding claim 7, Li et al. teach, wherein the second magnetic tunnel junction element further includes a through-hole extending therethrough (see Fig. 2-3, 4 and paragraph 0028-0038, 0036-0055, 0057-0063). Regarding claim 8, Li et al. teach, wherein the second magnetic tunnel junction element includes a first magnetic pattern, a second magnetic pattern, and a tunnel barrier pattern between the first magnetic pattern and the second magnetic pattern, and wherein a magnetization direction of the first magnetic pattern and a magnetization direction of the second magnetic pattern are parallel to each other (see Fig. 2-3, 4 and paragraph 0028-0038, 0036-0055, 0057-0063, 0065-0067). Regarding claim 9, Li et al. teach, wherein the word-line and the metal word-line are spaced apart in a first direction, wherein the metal word-line includes a first metal word-line and a second metal word- line, wherein a vertical level in the first direction from the word-line of the first metal word- line is lower than a vertical level in the first direction from the word-line of the second magnetic tunnel junction element, and wherein a vertical level of the second metal word-line in the first direction from the word-line is higher than the vertical level in the first direction from the word-line of the second magnetic tunnel junction element (see Fig. 2-3, 4 and paragraph 0028-0038, 0036-0055, 0057-0063, 0065-0069, 0081-0086). Regarding claim 10, Li et al. teach, wherein the vertical level of the second metal word-line in the first direction from the word-line is higher than a vertical level of the bit-line (see Fig. 2-3, 4 and paragraph 0028-0038, 0036-0055, 0057-0063, 0065-0066). Regarding claim 11, Li et al. teach, wherein the metal word-line further includes a third metal word-line, and wherein a vertical level in the first direction from the word-line of the third metal word- line is lower than the vertical level in the first direction from the word-line of the second metal word-line (see Fig. 2-3, 4 and paragraph 0028-0038, 0036-0055, 0057-0063). Regarding independent claim 12, Li et al. teach a magnetic memory device comprising: a substrate including a sub-memory cell array and a dummy area; a gate line on the substrate; a first magnetic tunnel junction element on a portion of the gate line on the sub-memory cell array (see Fig. 2-3, 4 and paragraph 0028-0038, 0036-0055, 0057-0063, 0065-0069, 0081-0086, 220 MTJ element, BL is bitline, WL is word-line, 405 substrate, 410 cell area structure, 414+418 dummy area structure); a second magnetic tunnel junction element on a portion of the gate line on the dummy area; and a metal word-line on the gate line, wherein the portion of the gate line on the dummy area is electrically connected to the second magnetic tunnel junction element and the metal word-line (see Fig. 2-3, 4 and paragraph 0028-0038, 0036-0055, 0057-0063, 0065-0069, 0081-0086, wordline coupled to dummy structure area, 414, 418 include second memory element of dummy area). Even though Li et al. teach wordline both for normal cell and dummy cell but silent exclusively about metal word-line. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Li et al. where gate of transistor dummy cell coupled to wordline through metal line which would be called metal wordline in order to effectively control and improve the device with reduced electromagnetic interference (see paragraph 0004). Regarding claim 13, Li et al. teach, further comprising a third magnetic tunnel junction element on the dummy area of the substrate and spaced apart from the second magnetic tunnel junction element, and wherein on the dummy area, the word-line is electrically connected to the third magnetic tunnel junction element (see Fig. 2-3, 4 and paragraph 0028-0038, 0036-0055, 0057-0063, 0065-0066). Regarding claim 14, Li et al. teach, wherein a width of the second magnetic tunnel junction element is different from a width of the first magnetic tunnel junction element in an elongate direction of the gate line and the metal word-line (see Fig. 2-3, 4 and paragraph 0028-0038, 0036-0055, 0057). Regarding claim 15, Li et al. teach, wherein the second magnetic tunnel junction element is configured in a short-circuited state (see Fig. 2-3, 4 and paragraph 0028-0038, 0036-0055, 0057-0063, 0065-0069, 0081-0086). Regarding claim 16, Li et al. teach, wherein the second magnetic tunnel junction element includes a first magnetic pattern, a second magnetic pattern, and a tunnel barrier pattern between the first magnetic pattern and the second magnetic pattern, wherein a magnetization direction of the first magnetic pattern and a magnetization direction of the second magnetic pattern are parallel to each other (see Fig. 2-3, 4 and paragraph 0028-0038, 0036-0055, 0057-0063, 0065-0069, 0081-0086). Regarding claim 17, Li et al. teach, wherein the gate line and the metal word-line are spaced apart in a first direction, wherein the metal word-line includes a first metal word-line and a second metal word- line, wherein a vertical level in the first direction from the substrate of the first metal word- line is higher than a vertical level in the first direction from the substrate of the second magnetic tunnel junction element, and wherein a vertical level in the first direction from the substrate of a second metal word- line disposed is lower than the vertical level in the first direction from the substrate of the second magnetic tunnel junction element (see Fig. 2-3, 4 and paragraph 0028-0038, 0036-0055, 0057-0063, 0065-0069, 0081-0086). Regarding independent claim 18, Li et al. teach a magnetic memory device comprising: a substrate including a sub-memory cell array and a dummy area; a bit-line and a word-line on the substrate; a memory cell on the sub-memory cell array of the substrate (see Fig. 2-3, 4 and paragraph 0028-0038, 0036-0055, 0057-0063, 0065-0069, 0081-0086, 405 substrate, 410 cell area structure, 414+418 dummy area structure), wherein the memory cell includes a first memory element connected to the bit-line, and a select transistor connected to the first memory element and having a gate connected to the word-line (see Fig. 2-3, 4 and paragraph 0028-0038, 0036-0055, 0057-0063, 0065-0069, 0081-0086, 220 MTJ element, BL is bitline, WL is word-line); a metal word-line on the word-line; and a second memory element on the dummy area of the substrate, wherein the word-line on the dummy area is electrically connected to the second memory element and the metal word-line (see Fig. 2-3, 4 and paragraph 0028-0038, 0036-0055, 0057-0063, 0065-0069, 0081-0086, wordline coupled to dummy structure area, 414, 418 include second memory element of dummy area). Even though Li et al. teach wordline both for normal cell and dummy cell but silent exclusively about metal word-line. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Li et al. where gate of transistor dummy cell coupled to wordline through metal line which would be called metal wordline in order to effectively control and improve the device with reduced electromagnetic interference (see paragraph 0004). Regarding claim 19, Li et al. teach, wherein each of the first memory element and the second memory element includes a magnetic tunnel junction element (see Fig. 2-3, 4 and paragraph 0028-0038, 0036-0055, 0057-0063, 0065-0069, 0081-0086). Regarding claim 20, Li et al. teach, wherein the word-line and the metal word- line are spaced apart in a first direction, wherein the metal word-line includes a first metal word-line and a second metal word- line, wherein a vertical level in the first direction from the substrate of the first metal word- line is lower than a vertical level in the first direction from the substrate of the bit-line, and wherein a vertical level in the first direction from the substrate of a second metal word- line disposed is higher than the vertical level in the first direction from the substrate of the bit- line (see Fig. 2-3, 4 and paragraph 0028-0038, 0036-0055, 0057-0063, 0065-0069, 0081-0086). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment. Any inquiry concerning this communication or earlier communications from the examiner should be directed to whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
Read full office action

Prosecution Timeline

Jan 16, 2025
Application Filed
Jun 29, 2026
Non-Final Rejection mailed — §103
Jul 30, 2026
Examiner Interview Summary
Jul 30, 2026
Applicant Interview (Telephonic)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12749551
SEMICONDUCTOR SYSTEM FOR DETECTING FAIL LOCATION
2y 6m to grant Granted Sep 29, 2026
Patent 12744104
APPARATUSES, SYSTEMS, AND METHODS FOR STORING MEMORY METADATA
2y 7m to grant Granted Sep 22, 2026
Patent 12744064
MEMORY DEVICE RELATED TO SIGNAL TRANSMISSION
2y 2m to grant Granted Sep 22, 2026
Patent 12731643
METHOD AND SYSTEM FOR ADJUSTABLE TOP SELECT GATE CONTROL
3y 5m to grant Granted Sep 08, 2026
Patent 12731653
NON-VOLATILE MEMORY SYSTEM AND DATA RECOVER READ OPERATION METHOD THEREOF
2y 2m to grant Granted Sep 08, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
95%
Grant Probability
98%
With Interview (+3.3%)
1y 10m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 674 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month