DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Figures 1, 2, 3A, and 3B should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The abstract of the disclosure is objected to because line 1 states, "The present disclosure provides . . ." (emphasis added). A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The disclosure is objected to because of the following informalities:
Line 20 on page 4, should read as, “. . . [[that]] than that of the SRAM including sixteen transistors (16T), . . .”
Appropriate correction is required.
Claim Objections
Claims 6, 8, and 9 is objected to because of the following informalities:
Claim 6 recites the limitation "the selecting" in line 18 in page 3 and claim 8 recites the limitation "the selecting" in line 24 of page 3. It is understood, “the selecting” refers to “selecting information to be written to the 4T TCAM cell,” however, it is best use the full length descriptor to maintain consistency and clarity and avoid indefiniteness in the claims. Please see the recommended amendments to the claims under the Claim Rejections - 35 USC § 112 section below.
Claim 9, line 15 of page 4, should read as, “. . . and applying a voltage corresponding to [[‘1’]] ‘0’ to the reverse . . .”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 6-9 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 6, 8, and 9 inconsistently refer to the limitation “selecting information to be written” recited in line 14 of page 3, in several different forms (i.e. “the information selected,” “information to be stored,” and “the information”) resulting in ambiguity in the antecedent basis and the intended distinction, if any. Presuming there isn’t a distinction in the information to be written, the selected information, and the information to be stored these terms should all be consistent to avoid they ambiguity. Please see the recommended amendments of claims 6, 8, and 9 below.
Claim 6 recites the limitation "the information selected" in line 17 of page 3. There is insufficient antecedent basis for this limitation in the claim. See recommended amendment below.
Claims 7-9 are rejected because they depend on claim 6; therefore, claims 7-9 contain at least the same defect(s).
Claim 8 recites the limitation "the primary deciding" in line 6 of page 4. There is insufficient antecedent basis for this limitation in the claim. See recommended amendment below.
Claim 9 recites the limitation "the primary deciding" in line 13 of page 4. There is insufficient antecedent basis for this limitation in the claim. See recommended amendment below.
Claim 9 recites the limitation "the secondary deciding" in lines 17 and 21 of page 4. There is insufficient antecedent basis for this limitation in the claim. See recommended amendment below.
Claim 6 is recommended to read as:
A method for writing information to the 4T TCAM cell of claim 4, comprising:
activating the word line;
selecting information to be written to the 4T TCAM cell; and
writing the information to be written to the 4T TCAM cell by applying voltages to the bit line and the reverse bit line according to the information to be written .
Claim 8 is recommended to read as:
The method of claim 7, wherein the selecting information to be written to the 4T TCAM cell includes:
primarily deciding whether or not the information to be written to the 4T TCAM cell is '0'; and
secondarily deciding whether or not the information to be written to the 4T TCAM cell is '1' when it is primarily decided that the information to be written to the 4T TCAM cell is not '0' .
Claim 9 is recommended to read as:
The method of claim 8, wherein the writing [[of]] the information to be written to the 4T TCAM cell includes:
applying a voltage corresponding to '0' to the bit line and applying a voltage corresponding to '1' to the reverse bit line when it is primarily decided that the information to be stored in the 4T TCAM cell is '0' ;
applying a voltage corresponding to '1' to the bit line and applying a voltage corresponding to [['1']] ‘0’ to the reverse bit line when it is secondarily decided that the information to be stored in the 4T TCAM cell is '1' ; and
applying voltages corresponding to '1' to the bit line and the reverse bit line when it is secondarily decided that the information to be stored in the 4T TCAM cell is neither '0' nor '1' .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (WO 2024250227 A1; hereinafter "Zhang") in view of Tseng et al. (US 20240265966 A1; hereinafter “Tseng”).
Regarding claim 1, Zhang teaches a 4T ternary content addressable memory (TCAM) cell (para. [0052]: “By using four transistors, the writing and searching function of the TCAM can be implemented, . . .”) connected to one word line, one match line, a bit line, a reverse bit line, a search line, and a reverse search line (FIG. 11: word line WL, match line ML, first bit line BL0, second bit line BL1, first source line SL0, and second source line SL1), comprising: a first write transistor that is a single-gate transistor (FIG. 11: first write transistor Tw1); a second write transistor that is a single-gate transistor (FIG. 11: second write transistor Tw2); a first read transistor that is a dual-gate transistor (FIG. 11: first dual-gate transistor Ts1); and a second read transistor that is a dual-gate transistor (FIG. 11: second dual-gate transistor Ts2), wherein the first read transistor, the second read transistor, are implemented as oxide semiconductors (see para. [0051] with respect the first and second read transistors: “In the storage unit of the present application, the dual-gate transistor may be a transistor of an oxide semiconductor material”; see para. [0053-0054] with respect to the first and second write transistors: “. . . both the first write transistor Tw1 and the second write transistor Tw2 may be NMOS (N-type metal-oxide-semiconductor) transistors, . . .”).
Zhang teaches the first and second write transistors Tw1, Tw2 may be NMOS transistors but does not explicitly express that they may be “oxide semiconductors” as interpreted by the limitation expressed in claim 1 (i.e., an IGZO oxide semiconductor as disclosed in para. [0008] of the present application).
Tseng, in the same field of endeavor, discloses a 2T0C TCAM memory cell structure (FIG.1) comprising write transistors WT0, WT1 which “could be indium gallium zinc oxide (IGZO), poly-silicon, amorphous silicon (a-Si) or polycrystalline germanium (poly-Ge) to make the leakage currents lwk of the write transistors WT0, WT1 as low as possible.” (Tseng at para. [0036]). The present application recognizes 2T0C TCAM oxide semiconductors as prior art (see FIG. 2 and paras. [0009-0013])—further affirming write transistors of TCAM cells are known in the art to implement oxide semiconductor materials. Moreover, NMOS transistors are known in the art to implement IGZO oxide semiconductors (see para. [0035] of Osawa et al. (US 20150055051 A1)) and there isn’t sufficient evidence to suggest the first and second write transistors Tw1, Tw2 of Zhang may not be NMOS transistors comprised of an oxide semiconductor material (i.e. IGZO).
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have modified or presumed the first and second write transistors Tw1, Tw2 of Zhang to include oxide semiconductor material, as taught by Tseng, because (1) Zhang discloses this design characteristic with respect to the first and second dual gate transistors Ts1, Ts2 and (2) 2T0C TCAM cells are well known in the art to include write transistors including oxide semiconductor materials. One of ordinary skill in the art would have been motivated to make this modification for the benefit of minimizing the leakage current from the storage node, e.g. “the quiescent current of the transistor being extremely small” (Zhang at Abstract); and “As the leakage currents lwk of the write transistors WT0, WT1 are low, the voltages stored at the storage nodes SN, SN′ could be retained well.” (Tseng at para. [0036]).
Regarding claim 2, Zhang discloses the dual- gate transistor includes a bottom gate terminal and a top gate terminal (FIG. 8: see the shaded regions of source line SL0 and storage node SN0).
Regarding claim 3, Zhang discloses the first write transistor has one terminal connected to the bit line (FIG. 11: first write transistor Tw1 and first bit line BL0) and a gate terminal connected to the word line (FIG. 11: word line WL), the second write transistor has one terminal connected to the reverse bit line (FIG. 11: second write transistor Tw2 and second bit line BL1) and a gate terminal connected to the word line (FIG. 11: word line WL), the first read transistor has one terminal connected to the match line (FIG. 11: first dual gate transistor Ts1 and match line ML), the other terminal connected to a ground voltage (FIG. 11: ground wire GND), a top gate terminal connected to the search line (FIG. 11: first source line SL0), and a bottom gate terminal connected to the other terminal of the first write transistor (FIG. 11: the connection between the first dual gate transistor Ts1 and the first write transistor Tw1), and the second read transistor has one terminal connected to the match line (FIG. 11: second dual gate transistor Ts2 and match line ML), the other terminal connected to the ground voltage (FIG. 11: ground wire GND), a top gate terminal connected to the reverse search line (FIG. 11: second source line SL1), and a bottom gate terminal connected to the other terminal of the second write transistor (FIG. 11: the connection between the second dual gate transistor Ts2 and the second write transistor Tw2).
Regarding claim 4, Zhang discloses the first write transistor has one terminal connected to the bit line (FIG. 11: first write transistor Tw1 and first bit line BL0) and a gate terminal connected to the word line (FIG. 11: word line WL), the second write transistor has one terminal connected to the reverse bit line (FIG. 11: second write transistor Tw2 and second bit line BL1) and a gate terminal connected to the word line (FIG. 11: word line WL), the first read transistor has one terminal connected to the match line (FIG. 11: first dual gate transistor Ts1 and match line ML), the other terminal connected to a ground voltage (FIG. 11: ground wire GND), a gate terminal connected to the search line (FIG. 11: first source line SL0), and a [[top]] gate terminal connected to the other terminal of the first write transistor (FIG. 11: the connection between the first dual gate transistor Ts1 and the first write transistor Tw1), and the second read transistor has one terminal connected to the match line (FIG. 11: second dual gate transistor Ts2 and match line ML), the other terminal connected to the ground voltage (FIG. 11: ground wire GND), a gate terminal connected to the reverse search line (FIG. 11: second source line SL1), and a [[top]] gate terminal connected to the other terminal of the second write transistor (FIG. 11: the connection between the second dual gate transistor Ts2 and the second write transistor Tw2).
That is, Zhang teaches a first gate configuration for the dual-gate transistors (i.e., the first and second read transistors in the present application) wherein the top and bottom gate connections are consistent with the limitations recited in claim 3 and FIG. 4 of the present application.
However, Zhang is silent with respect to a second gate configuration of the dual-gate transistors wherein the top and bottom gate connections are exchanged, as expressed in claim 4 and illustrated in FIG. 5 of the present application. Regardless, Zhang discloses the essential structures (i.e., the first and second dual-gate transistors Ts1, Ts2) of the TCAM cell recited in the present application and it is apparent the dual-gate transistors must inconsequentially perform the intended function with either the first or the second gate configuration—otherwise, one of the first or second gate configurations would render the device inoperable or with undesirable performance in the present application.
Therefore, the second gate configuration of the dual-gate transistors recited in claim 4 is interpreted to be merely a design choice since the applicant has not disclosed the gate configuration solves any stated problem nor serves a particular purpose, and it appears that the invention would perform equally well with either the first or second gate configurations recited in claims 3 and 4, respectively. Moreover, It would have been obvious to a person having ordinary skill in the at the time the invention was made to use the second gate configuration of the dual-gate transistors recited in claim 4 since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70).
Regarding claim 5, Zhang discloses a 4T TCAM cell array comprising: a plurality of 4T TCAM cells of wherein each of the plurality of the 4T TCAM cells is connected to one word line, one match line, a bit line, a reverse bit line, a search line, and a reverse search line (FIG. 13 illustrates a top view of an array of the memory cells depicted in FIGs. 11 and 12).
Regarding claim 6, Zhang discloses A method for writing information to the 4T TOAM cell of claim 4, comprising: activating the word line; selecting information to be written to the 4T TCAM cell; and writing information to the 4T TOAM cell by applying voltages determined according to the information selected in the selecting to the bit line and the reverse bit line (para. [0025]: “ In response to the write instruction, the process of specifically performing the write operation is as follows: first, the selected word line is controlled to be set to the first voltage, for example, set to "1", so as to control the first write transistor and the second write transistor connected to the selected word line to be turned on, . . . After that, the plurality of first bit lines and the plurality of second bit lines are controlled to be set to a first voltage, for example, "1" or a second voltage, for example, set to "0".”).
Regarding claim 7, Zhang discloses the information to be written to the 4T TOAM cell is '0', '1', and "don't care X" (Table 2 and para. [0064]: “Referring to Table 2, when the data needing to be searched is "0", the first source line SL0 and the second source line SL1 respectively input "0" and "1"; when the data to be searched is defined as "1", the first source line SL0 and the second source line SL1 respectively input "1" and "0"; and the first source line SL0 and the second source line SL1 are both input to "0" if it is defined that regardless of the value of a certain bit (the mask bit is "X" data).”).
Regarding claim 8, Zhang discloses the selecting includes: primarily deciding whether or not information to be stored in the 4T TCAM cell is '0'; and secondarily deciding whether or not the information to be stored in the 4T TCAM cell is '1' when it is decided that the information to be stored in the 4T TCAM cell is not '0' in the primary deciding (Table 1 and para. [0061]: “Referring to Table 1, when the data to be written is defined as "0", the first storage node SN 0 and the second storage node SN 1 are written to "0" and "1", respectively; when the data to be written is defined as "1", the first storage node SN 0 and the second storage node SN 1 are respectively written into "1" and "0".”).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (WO 2024250227 A1; hereinafter "Zhang") as applied to claims 4 and 6-8 above, and further in view of Louie et al. (US 20140198551 A1; hereinafter "Louie").
Regarding claim 9, Zhang discloses the writing of the information to the 4T TCAM cell includes: applying a voltage corresponding to '0' to the bit line and applying a voltage corresponding to '1' to the reverse bit line when it is decided that the information to be stored in the 4T TCAM cell is '0' in the primary deciding (para. [0061]: “Referring to Table 1, when the data to be written is defined as "0", the first storage node SN0 and the second storage node SN1 are written to "0" and "1", respectively . . . the plurality of first bit lines BL0 and the plurality of second bit lines BL1 are controlled according to the data to be written into the first voltage, for example, "1" or the second voltage is set to "0" according to Table 1.”); applying a voltage corresponding to '1' to the bit line and applying a voltage corresponding to '1' to the reverse bit line when it is decided that the information to be stored in the 4T TCAM cell is '1' in the secondary deciding (para. [0061]: “. . . when the data to be written is defined as "1", the first storage node SN 0 and the second storage node SN 1 are respectively written into "1" and "0". . . the plurality of first bit lines BL 0 and the plurality of second bit lines BL 1 are controlled according to the data to be written into the first voltage, for example, "1" or the second voltage is set to "0" according to Table 1.”).
However, Zhang is silent with respect to applying voltages corresponding to ‘1’ to the bit line and the reverse bit line when it is decided that the information to be stored in the 4T TCAM cell is neither '0' nor '1' in the secondary deciding. According to Table 2, Zhang suggests the “don’t care” value denoted by the first and second storage nodes with a ‘0’ and ‘0’; but Table 2 defines the source line inputs during a search operation (see also para. [0064]: “. . . the first source line SL0 and the second source line SL1 are both input to "0" if the value of the non-pipe bit (the mask bit is "X" data)”).
Louie, in the same field of endeavor, teaches “. . . storing a "don't care" state within the TCAM memory, the user or system should also have the ability to mask or apply a "don't care" state when applying match data to the TCAM memory. This function is typically implemented by using a normally illegal state of non-complementary data such as "11" or "00" instead of the typically complementary data of "10" or "01".” (see Louie at para. [0012])
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the TCAM cell in FIG. 11 of Zhang to associate a non-complementary data value of “11” with the “don’t care” or “X” value, store that value in the storage nodes SN0, SN1, respectively, and require applying voltages corresponding to ‘1’ to both the first and second bit lines BL0, BL1, as suggested by the teachings of Louie. One of ordinary skill in the art would have been motivated to make this modification for the benefit of modifying a content addressable memory to support an additional “don’t care” or “x” state beyond traditional “1” and “0” states with illegal non-complementary data states (Louie at para. [0012]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUSTIN BRYCE HEISTERKAMP whose telephone number is (703)756-1095. The examiner can normally be reached M-F 0800-1700.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUSTIN BRYCE HEISTERKAMP/Examiner, Art Unit 2827 /AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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