CTNF 19/024,829 CTNF 92582 DETAILED ACTION This action is responsive to the preliminary amendment filed 4/4/2025. Claims 1-20 are pending and have been examined. Claims 1, 4-5, 10, 12-13, 16 and 18-19 have been amended. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The examiner suggests amending title to include details of the regioning support. Claim Objections 07-29-01 AIA Claim s 3-4 and 11-12 objected to because of the following informalities: In regards to claim 3, line 2 amend “the single clock…” to “a single clock” as to correct a minor antecedent basis issue as there is no prior recitation of “a single clock cycle”. In regards to claim 11, line 2 amend “the single clock…” to “a single clock” as to correct a minor antecedent basis issue as there is no prior recitation of “a single clock cycle”. Claims 4 and 12 are dependent upon one of the claims above and therefore are similarly objected to for including the deficiencies of one of the claims above . Appropriate correction is required. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-36 AIA Claim s 1, 3-4, 10-12 and 16-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1, 3, 9-10 and 14-16 of U.S. Patent No. 12,236,238 in view of Wang, PGPUB No. 2021/0109761 . Claim 3, which includes all limitations of claim 1, of USPAT No. 12,236,238 mostly anticipates claim 1 of claim the instant application. However, claims 1 and 3 of USPAT No. 12,236,238 do not disclose “providing regioning support to enable access between channels of a float pipe”. Wang discloses providing regioning support to enable access between channels of a float pipe ([abstract, 0031, 0034, 0072]: wherein operand sharing enables access between SIMD lanes in a floating-point execution pipeline) It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the regioning support of USPAT No. 12,236,238 to enable access between channels of a float pipe as taught in Wang. It would have been obvious to one of ordinary skill in the art because enabling access between lanes as disclosed in Wang can improve performance and power consumption for operations (Wang [abstract and 0032-0033]) . Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. 07-34-03 AIA The term “ large ” in claim s 1-2, 10 and 16-17 is a relative term which renders the claim indefinite. The term “ large ” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Based on the above term the limitation stating “large integer multiplication” is indefinite because it is unclear what a large “integer multiplication” means. For example, is large referring to a bit size (e.g. a 512-bit) of operands used in a multiplication, a multiplication that requires multiple clock cycles to compute or a multiplication using large inputs (e.g. data set sizes or matrices of a defined size)? In regards to claim 4, the limitation stating “…an upper 32-bits of an element for multiplication with a lower 32-bits of the element ” lacks clarity in light of the specification. The limitation lacks clarity because from the specification Figs. 30-32 depict multiplying portions of operand A0xB0, wherein A0 is stored in a register and B0 is stored in a different register, such that an upper portion of A0 would be selected for multiplication with a lower portion of B0 or vice versa, e.g. a different element. Thus, the claim limitation lacks clarity because it appears applicant is stating that to perform the multiplication a lower portion of A0 would be multiplied with an upper portion of A0 (wherein A is a same element), which appears to be inconsistent with the multiplication operations disclosed in Figs. 30-32. For purpose of examination the examiner will interpret the limitation as the former. Additionally, the examiner asserts if the applicant believes the current language is correct the examiner requests the applicant explain in detail the claim limitation using discussion from the specification. Claims 12 and 18 are similarly rejected on the same basis as claim 4 above. Claims 2-9, 11-15 and 17-20 are dependent upon one or more claims above and therefore are similarly rejected for including the deficiencies of one or more claims above . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-4, 7-12 and 15-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang, PGPUB No. 2021/0109767, and further in view of Anderson, USPAT No. 8,918,445 (cited on IDs filed on 4/4/2025) . In regards to claim 1, Wang discloses A processor ([0022 and Figs. 1A, 2 and 10) comprising: processing resources comprising multiplier circuitry to: receive operands for a multiplication operation using at least one multiply and add (MAD) instruction utilizing a multiplier ([0025 and 0034]: wherein circuitry (combination of routing circuitry and execution circuitry) receives operands for at least one multiply add instruction) wherein the multiplication operation is part of a chain of multiplication operations for a large multiplication ([0025, 0034 and abstract]: wherein the multiply add operation is a part of a chain of multiplication operations for a larger single matrix multiply operation (also see [0039-0071 and Figs. 5A-D] which discloses multiple multiply add operations used to perform a single matrix multiply operation)) provide regioning support to enable access between channels of a float pipe that is to execute the at least one MAD instruction ([abstract, 0031, 0034 and 0072-0074]: wherein operand sharing (e.g. regioning) between lanes of floating point pipeline circuitry is used to execute at least one multiply add operation (See Figs. 5A-D)) and generate an output from the at least one MAD instruction that utilizes the multiplier and the regioning support ([0072-0074]: wherein outputs are generated from at least one multiply add operation that utilizes floating-point circuitry and operand sharing between lanes supported by routing circuitry (also see [0039-0071 and Figs. 5A-D] for further clarity on multiply-add operations and generated outputs)) Wang does not explicitly disclose comprising multiplier circuitry to: receive operands for a multiplication operation using at least one multiply and add (MAD) instruction utilizing a double precision multiplier for an integer multiplication. Wang does disclose using fused multiply multiplication circuitry to perform large floating-point multiply operations and other embodiments that may include integer multiplication circuitry to perform large integer operations using different data formats (Wang [0034]). However, Wang does not disclose using multiplier circuitry that uses a double precision multiplier nor using a float pipe (floating-point circuitry) to perform integer operations. Anderson discloses comprising multiplier circuitry to: receive operands for a multiplication operation using at least one multiply and add (MAD) instruction utilizing a double precision multiplier for an integer multiplication in a float pipe (abstract, Column 6, lines 1-56 and Column 8, lines 35-39: wherein multiplier circuitry receives operands for multiplication operations which may include dot product operations (multiply and add operations) utilize a double precision multiplier which performs integer operations in a float pipe. Wherein the multiplier clusters perform floating point operations and thus are considered float pipes (See Fig. 5A-B)) It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the large multiplication of Wang to be an integer multiplication operation as taught in Anderson. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (performing an integer multiplication as taught in Anderson) for another (performing floating-point multiplication as taught in Wang) to yield predictable results (performing a large integer multiplication) (MPEP 2143, Example B). Additionally, this can provide added flexibility to a processor by performing operations on various data types. It would have then been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the floating-point multiplier circuitry of Wang to include a double precision multiplier to perform integer multiplication operations as the floating-point multiplier circuitry of Anderson. It would have been obvious to one of ordinary skill in the art because using a single computational unit to perform operations on integer and floating-point data formats of various sizes optimizes circuit implementation and minimizes circuit area (Anderson: Column 1, lines 30-35). Claim 16 is similarly rejected on the same basis as claim 1 above as claim 16 is the system claim corresponding to the processor of claim 1 above. (Note: Wang discloses “A system comprising a memory to store a block of data and a processor coupled to the memory” (See Fig. 10)) In regards to claim 2, the combination of Wang and Anderson discloses The processor of claim 1 (see rejection of claim 1 above) wherein the multiplier circuitry is further to: combine a result of the MAD instruction with results of other MAD instructions to generate a final result for the large integer multiplication (Wang [0038-0039 and 0056-0071] (also see 0040-0055 for further details on multiply add operations)) and output the final result for the large integer multiplication (Wang [0039 and 0070-0072]: wherein the final result of the large multiplication is stored in R15) Claim 10 is similarly rejected on the same basis as claim 2 above as claim 10 is the method claim corresponding to the processor claim 2 above. Claim 17 is similarly rejected on the same basis as claim 2 above as claim 17 is the system claim corresponding to the processor of claim 2 above. In regards to claim 3, the combination of Wang and Anderson discloses The processor of claim 1 (see rejection of claim 1 above) wherein the MAD instruction utilizing the double precision multiplier generates a 64-bit output (Anderson: abstract, Column 6, lines 1-56 and Column 8, lines 35-39 (See Figs. 5A-B)) The combination of Wang and Anderson thus far does not explicitly disclose generating a 64-bit output in the single clock cycle. However, Anderson does disclose generating an output for instructions in a single clock cycle (Column 4, lines 1-12) It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the generation of a 64-bit output to be generated in a single clock cycle as the other single cycle instructions taught in Anderson. It would have been obvious to one of ordinary skill in the art because it would increase processor performance and efficiency by producing 64-bit results faster. Claim 11 is similarly rejected on the same basis as claim 3 above as claim 11 is the method claim corresponding to the processor claim 3 above. In regards to claim 4, the combination of Wang and Anderson discloses The processor of claim 3 (see rejection of claim 3 above) wherein the multiplier circuitry comprises one or more multiplexors to support the regioning for the MAD instruction (Wang [0091-0094 and See Figs 1 A and 2]: wherein routing circuits (of multiplier circuitry interpreted to be combination of execution circuitry and routing circuitry) comprises multiplexers to support operand sharing for fused multiply-add instructions) utilizing the double precision multiplier (Anderson: abstract, Column 6, lines 1-56 and Column 8, lines 35-39: wherein multiplier circuitry receives operands for multiplication operations which may include dot product operations (multiply and add operations) utilize a double precision multiplier) the regioning comprising the multiplier circuitry to access, using the one or more multiplexors, an upper 32-bits of an element for multiplication with a lower 32-bits of the element. (Wang [0033-0072]: discloses using the routing circuitry to access upper bits of elements to multiply with lower bits of elements | Anderson: Column 6, lines 55-62 and Column 7, lines 14-35 and Column 8, lines 30-40: which discloses multiplying 32x32 bit data. (note the combination of references discloses the above limitation)) Claim 12 is similarly rejected on the same basis as claim 4 above as claim 12 is the method claim corresponding to the processor claim 4 above. Claim 18 is similarly rejected on the same basis as claim 4 above as claim 18 is the system claim corresponding to the processor of claim 4 above. In regards to claim 7, the combination of Wang and Anderson discloses The processor of claim 1 (see rejection of claim 1 above) wherein the multiplier circuitry comprises a plurality of adders and shifters. (Anderson: Column 6, lines 55-62 and Column 7, lines 14-35: wherein a multiplier comprising adders and shifters (multiplexers) is disclosed (See Figs. 5A-B and claim 2)) The combination of Wang and Anderson thus far does not disclose a multiplier is part of an arithmetic logic unit (ALU). However, Anderson discloses a processor comprising an ALU and a multiplier (Column 1, lines 64-67) Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify multiplier circuitry of Wang and Anderson to be a part of a ALU as taught in Anderson. It would have been obvious to one of ordinary skill in the art because including an ALU in a processor can increase processor performance by adding capabilities to do additional logical operations (e.g. AND, NOT, XOR, etc.). Furthermore, it would have been obvious because it would be seen as an integration of parts (e.g. including a multiplier circuit as a part of an ALU), which the courts have deemed obvious (See MPEP 2144.04(V)(B)). Claim 15 is similarly rejected on the same basis as claim 7 above as claim 15 is the method claim corresponding to the processor claim 7 above. In regards to claim 8, the combination of Wang and Anderson discloses The processor of claim 1 (see rejection of claim 1 above) wherein the processor comprises a graphics processing unit (GPU). (Wang [0022 and 0103]) In regards to claim 9, the combination of Wang and Anderson discloses The processor of claim 1 (see rejection of claim 1 above) wherein the processor is at least one of a single instruction multiple data (SIMD) machine or a single instruction multiple thread (SIMT) machine. (Wang [0022 and 0103-0104]) Allowable Subject Matter 07-43-02 AIA Claim s 5-6, 13-14 and 19-20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: The prior art of record, alone or in combination, fail to disclose or render obvious claim 5 filed on 4/4/2025. The prior art of record has not taught either individually or in combination and together with all other claimed features “The processor of claim 1, wherein the MAD instruction is further to utilize a 48-bit output to combine with a multiply and accumulate high (MACH) instruction to generate a 64-bit result, and wherein the MACH instruction to write an upper 32- bits of the 64-bit result to a register and carry a lower 32-bits of the 64-bit result to a chained MAD instruction that outputs another 48-bit result” as claimed in claim 5. The closest prior art of record, Donofrio (USPAT No. 2007/0074008 cited on IDS filed on 4/4/2025) discloses generating a 48-bit output using a MAD instruction. While, Mimar (USPAT No. 7,873,812) discloses a vector accumulator storing 48-bit vector elements. However, neither reference discloses “…wherein the MAD instruction is further to utilize a 48-bit output to combine with a multiply and accumulate high (MACH) instruction to generate a 64-bit result, and wherein the MACH instruction to write an upper 32- bits of the 64-bit result to a register and carry a lower 32-bits of the 64-bit result to a chained MAD instruction that outputs another 48-bit result” as claimed. Furthermore, while some limitations may be broadly disclosed in the references above, the specific combination of limitations would not be obvious as claimed absent impermissible hindsight. Claims 13 and 19 are similarly allowable over the prior art for the same reason as claim 5 above . 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: The prior art of record, alone or in combination, fail to disclose or render obvious claim 6 filed on 4/4/2025. The prior art of record has not taught either individually or in combination and together with all other claimed features “processor of claim 1, wherein the multiplier circuitry is further to issue an add and accumulate (AAC) instruction in combination with the MAD instruction to accumulate a partial product generated by the MAD instruction, the AAC instruction to generate a 64-bit result with an upper 32-bits of the 64-bit result written to a register and a lower 32-bits of the 64-bit result remaining in an accumulator ” as claimed in claim 6. The closest prior art of record, Wang discloses using a sequence of accumulate instructions to generate 16-bit high and low portions of results using temporary accumulator registers and a result register. While, Raubuch (PGPUB No. 2012/0198212) discloses using multiply high and accumulate instructions which generate 64-bit results, wherein 32-high bits are written to a destination register and the lower bits are written into a register extension cache. However, neither reference discloses “…the AAC instruction to generate a 64-bit result with an upper 32-bits of the 64-bit result written to a register and a lower 32-bits of the 64-bit result remaining in an accumulator ” as claimed. Furthermore, while some limitations may be broadly disclosed in the references above, the specific combination of limitations would not be obvious as claimed absent impermissible hindsight. Claims 14 and 20 are similarly allowable over the prior art for the same reason as claim 6 above . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure : Chen (PGPUB No. 2019/0004814) for teaching cross lane sharing in a SIMD processor Raubuch (PGPUB No. 2012/0198212) discloses using multiply high and accumulate instructions which generate 64-bit results, wherein 32-high bits are written to a destination register and the lower bits are written into a register extension cache. Mimar (USPAT No. 7,873,812) discloses a vector accumulator and vector accumulator instructions Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY P SPANN whose telephone number is (571)431-0692. The examiner can normally be reached M-F, 9am-6pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /COURTNEY P SPANN/Primary Examiner, Art Unit 2183 Application/Control Number: 19/024,829 Page 2 Art Unit: 2183 Application/Control Number: 19/024,829 Page 3 Art Unit: 2183 Application/Control Number: 19/024,829 Page 4 Art Unit: 2183 Application/Control Number: 19/024,829 Page 5 Art Unit: 2183 Application/Control Number: 19/024,829 Page 6 Art Unit: 2183 Application/Control Number: 19/024,829 Page 7 Art Unit: 2183 Application/Control Number: 19/024,829 Page 8 Art Unit: 2183 Application/Control Number: 19/024,829 Page 9 Art Unit: 2183 Application/Control Number: 19/024,829 Page 10 Art Unit: 2183 Application/Control Number: 19/024,829 Page 11 Art Unit: 2183 Application/Control Number: 19/024,829 Page 12 Art Unit: 2183 Application/Control Number: 19/024,829 Page 13 Art Unit: 2183 Application/Control Number: 19/024,829 Page 14 Art Unit: 2183 Application/Control Number: 19/024,829 Page 15 Art Unit: 2183 Application/Control Number: 19/024,829 Page 16 Art Unit: 2183 Application/Control Number: 19/024,829 Page 17 Art Unit: 2183
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