Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chau et al (US PUB. 20220171373, herein Chau).
Regarding claim 1, Chau teaches A semiconductor processing system comprising: a plurality of processing modules in which a plurality of events for a wafer occur (0006);
and a processor configured to receive system data related to: i) a given event of the plurality of events (0006 “ instructions are configured to train a model using the first data and data generated by the simulation to predict optimum scheduling parameters for processing the semiconductor substrates in the plurality of processing chambers according to the recipe. The instructions are configured to receive inputs from the tool regarding processing of one of the semiconductor substrates in the plurality of processing chambers according to the recipe. The instructions are configured to predict based on the inputs, using the model, optimum scheduling parameters for processing the one of the semiconductor substrates in the plurality of processing chambers according to the recipe. The instructions are configured to schedule operations of the tool based on the optimum scheduling parameters for processing the one of the semiconductor substrates in the plurality of processing chambers according to the recipe.”)
and ii) the plurality of processing modules, wherein the processor is further configured to perform discrete event simulation of an order of occurrence of each event of the plurality of events (0164 “discrete event simulator 1202 can simulate a wafer processing sequence that takes about an hour in less than a minute. The discrete event simulator 1202 can simulate 1-level and 2-level wafer processing sequence as well as running WACs in PMs. The discrete event simulator 1202 includes a built in HTTP server based application programming interface (API) to facilitate information exchange between the discrete event simulator 1202 and the model 1204. The discrete event simulator 1202 outputs scheduling cycle information in JSON format via the API. The model 1204 processes the JSON file to select the next operation, which is returned to the discrete event simulator 1202 via the API”)
wherein the processor is further configured to:
select an end of at least one event that may occur after an earlier-ending event on the wafer as an event candidate of a plurality of event candidates using the system data, determine one of the plurality of event candidates as a selected event, store the selected event in an event queue, sequentially proceed with the selected event stored in the event queue, and delete the selected event whose progress has ended from the event queue and based on all selected events stored in the event queue being deleted, the processor is configured to terminate the discrete event simulation and output simulation result data (0169 “the discrete event simulator 1202 generates a set of all possible next scheduled level operations that can be performed by the tool to transition to the next state. At 1306, the discrete event simulator 1202 outputs the set of next scheduled level operations to the model 1204. At 1308, the model 1204 selects the best next operation to schedule that will provide the best system performance. At 1310, the model 1204 memorizes the best next operation to schedule for this tool state. At 1312, the discrete event simulator 1202 executes the best next operation to simulate the next state”, 0170 “the discrete event simulator 1202 determines whether the final state is reached. The discrete event simulator 1202 repeats steps 1304-1312 until the final state is reached. At 1316, after the final state is reached, the reinforcement training of the model 1204 is complete. At 1318, the model 1204 uses the memorized best next operation for each state when that particular state occurs in the tool during actual wafer processing. This way, using the model 1204, the tool always selects the best path in which to move a wafer through the tool for optimum throughput performance when transitioning from one state to another”).
Regarding claim 2, the cited prior art teach The semiconductor processing system of claim 1.
Chau teaches wherein the system data comprises at least one of a configuration of the plurality of processing modules, a relationship between the plurality of processing modules, a layout of the plurality of processing modules, a process recipe, time of the event, and a process parameter (0023 “the data generated by the simulation includes data generated based on the configuration of the tool, wafer-flow types, run scenarios, recipe times, and wafer-less auto clean times obtained from the tool.”)
Regarding claim 3, the cited prior art teach The semiconductor processing system of claim 2.
Chau teaches wherein the time of the event comprises an operation time of the plurality of processing modules according to the event and a movement time for the wafer to move between the plurality of processing modules (0023 “the data generated by the simulation includes data generated based on the configuration of the tool, wafer-flow types, run scenarios, recipe times, and wafer-less auto clean times obtained from the tool.”, 0091 “ each of the processing chambers 104 may be configured to perform one or more types of substrate treatment. In other words, the substrates may be loaded into one of the processing chambers 104, processed, and then moved to one or more other one of the processing chambers 104 (if at least one performs a different treatment) and/or removed from the substrate processing tool 100 (if all perform the same treatment).”)
Regarding claim 4, the cited prior art teach The semiconductor processing system of claim 2.
Chau teaches wherein the process parameter comprises at least one of RF power, fluid pressure, a fluid flow rate, chamber pressure, and temperature (0005 “a recipe defines sequencing, operating temperatures, pressures, gas chemistry, plasma usage, parallel modules, periods for each operation or sub-operation, substrate routing path, and/or other parameters. The substrates may be transferred between two or more processing chambers in a particular sequence to undergo different treatments.”, 0046 “controller is configured to predict, using a model trained by simulating the tool and the recipe, processing times for processing the semiconductor substrates in the plurality of processing chambers; transfer times for the second robot for transferring the semiconductor substrates between the plurality of processing chambers; a route to transfer the semiconductor substrates between the plurality of processing chambers based on the processing times and the transfer times; and a time when the first robot is to schedule additional semiconductor substrates for processing in the tool based on the processing times and the transfer times. Processing the semiconductor substrates according to the predicted route and processing the additional semiconductor substrates according to the predicted time optimizes wait times for the semiconductor substrates along the predicted route and optimizes throughput of the tool.”).
Regarding claim 5, the cited prior art teach The semiconductor processing system of claim 1.
Chau teaches wherein the processor is further configured to select, as the event candidate, at least one second event that may occur after a first event in progress on the wafer is completed, in consideration of a first state of the plurality of processing modules and a first state of the wafer (0198 “using a simulator, based on the obtained data, the method 1500 simulates various routing and scheduling scenarios for processing wafers. At 1506, using the simulator, the method 1500 simulates wafer processing using the various routing and scheduling scenarios.”, 0164 “discrete event simulator 1202 can simulate a wafer processing sequence that takes about an hour in less than a minute. The discrete event simulator 1202 can simulate 1-level and 2-level wafer processing sequence as well as running WACs in PMs. The discrete event simulator 1202 includes a built in HTTP server based application programming interface (API) to facilitate information exchange between the discrete event simulator 1202 and the model 1204. The discrete event simulator 1202 outputs scheduling cycle information in JSON format via the API. The model 1204 processes the JSON file to select the next operation, which is returned to the discrete event simulator 1202 via the API”).
Regarding claim 6, the cited prior art teach The semiconductor processing system of claim 1.
Chau teaches wherein the processor is further configured to determine one event exceeding a restriction condition among the plurality of event candidates as the selected event (0148).
Regarding claim 7, the cited prior art teach The semiconductor processing system of claim 6.
wherein the restriction condition comprises at least one of a failure of a processing module in which the event candidate occurs and introduction of another wafer into the processing module in which the event candidate occurs (0148 “Other validation methods can be used to validate the model. For example, an N-fold cross-validation method may be used. In this method, the total dataset is divided into one final test set and N other subsets, where N is an integer greater than one. Each model is trained on all but one of the subsets to get N different estimates of the validation error rate. The model with the lowest validation error rate is deployed for use”, 0181 “Accordingly, in the proposed method, a model for scheduler pacing is built using nested neural networks or other machine learning algorithms. The model is initially built, trained, and tested offsite using simulation. Subsequently, the model is continually refined and trained further onsite on the actual tool by incrementally using data streams from the tool to make further adjustments to the model that reflect the tool-specific and recipe-specific robot transfer times and that compensate for any process drift. The onsite training also adjusts the model for any recipe changes and/or tool hardware changes.”)
Regarding claim 8, the cited prior art teach The semiconductor processing system of claim 6.
Chau teaches wherein the processor is further configured to determine priority based on an end time of the selected event and stores the selected event in the event queue in order of high priority (0125 “model generator 408 may use other approaches instead of or in addition to the machine learning methods. Examples of other approaches include metaheuristic and mathematical methods (e.g., petri net). The metaheuristic method is a branch of artificial intelligence (AI) and is an automatic trial-and-error method to find a near-optimum scheduling pattern to meet pre-defined performance requirements. Scheduling parameter values can then be extracted from the selected scheduling pattern. Examples of algorithms used to find a near-optimum scheduling pattern include genetic algorithm and genetic programming.”, 0126).
Regarding claim 9, the cited prior art teach The semiconductor processing system of claim 1.
Chau teaches wherein the processor is further configured to store an end time of the selected event in the event queue along with the selected event (0169 “the discrete event simulator 1202 generates a set of all possible next scheduled level operations that can be performed by the tool to transition to the next state. At 1306, the discrete event simulator 1202 outputs the set of next scheduled level operations to the model 1204. At 1308, the model 1204 selects the best next operation to schedule that will provide the best system performance. At 1310, the model 1204 memorizes the best next operation to schedule for this tool state. At 1312, the discrete event simulator 1202 executes the best next operation to simulate the next state”, 0170 “the discrete event simulator 1202 determines whether the final state is reached. The discrete event simulator 1202 repeats steps 1304-1312 until the final state is reached. At 1316, after the final state is reached, the reinforcement training of the model 1204 is complete. At 1318, the model 1204 uses the memorized best next operation for each state when that particular state occurs in the tool during actual wafer processing. This way, using the model 1204, the tool always selects the best path in which to move a wafer through the tool for optimum throughput performance when transitioning from one state to another”).
Regarding claim 10, the cited prior art teach The semiconductor processing system of claim 1.
Chau teaches wherein the simulation result data comprises a start time and an end time of the selected event (0169 “the discrete event simulator 1202 generates a set of all possible next scheduled level operations that can be performed by the tool to transition to the next state. At 1306, the discrete event simulator 1202 outputs the set of next scheduled level operations to the model 1204. At 1308, the model 1204 selects the best next operation to schedule that will provide the best system performance. At 1310, the model 1204 memorizes the best next operation to schedule for this tool state. At 1312, the discrete event simulator 1202 executes the best next operation to simulate the next state”, 0170 “the discrete event simulator 1202 determines whether the final state is reached. The discrete event simulator 1202 repeats steps 1304-1312 until the final state is reached. At 1316, after the final state is reached, the reinforcement training of the model 1204 is complete. At 1318, the model 1204 uses the memorized best next operation for each state when that particular state occurs in the tool during actual wafer processing. This way, using the model 1204, the tool always selects the best path in which to move a wafer through the tool for optimum throughput performance when transitioning from one state to another”).
Claims 11-20 are rejected using similar reasoning as the rejection of claims 1-10 due to reciting similar limitations.
Conclusion
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/TAMEEM D SIDDIQUEE/
Primary Examiner
Art Unit 2116
