Prosecution Insights
Last updated: October 23, 2026
Application No. 19/025,221

SEMICONDUCTOR MEMORY DEVICE, CONTROLLER, AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE AND CONTROLLER

Non-Final OA §102
Filed
Jan 16, 2025
Priority
Mar 16, 2022 — RE 10-2022-0032965 +1 more
Examiner
NGUYEN, VAN THU T
Art Unit
2824
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK hynix Inc.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
803 granted / 968 resolved
+15.0% vs TC avg
Moderate +6% lift
Without
With
+6.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
32 currently pending
Career history
1006
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
45.9%
+5.9% vs TC avg
§102
32.3%
-7.7% vs TC avg
§112
14.8%
-25.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 968 resolved cases

Office Action

§102
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-6 are pending and examined. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: SEMICONDUCTOR MEMORY DEVICE AND METHOD OPERATING WITH GARBAGE COLLECTION POLICY. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 10,740,229 to Na et al. (hereafter Na). Regarding independent claim 1, Na teaches a method of operating a controller for controlling an operation of a semiconductor memory device including a plurality of pages, the method comprising: generating a command for checking a programmed page ratio among the plurality of pages (FIG. 1: sending Signaltrig to page counting unit 504 and obtaining number of program pages ΔPGM and total sum ΣΔVPC of valid page decrease for ratio calculation, see ); implicitly transmitting the command to the semiconductor memory device (FIG. 5: for the map updating unit 506 to update the address information of the user data programmed in the memory block, the memory controller 130 should send command to the memory 150 to request information, see 12:62-13:3); receiving information on the programmed page ratio from the semiconductor memory device (i.e. updated address information of the user data programmed in the memory block); and determining a garbage collection policy of the semiconductor memory device, based on the received information (FIG. 6: determining garbage collection policy in step S624). Regarding dependent claim 2, Na teaches wherein determining the garbage collection policy comprises determining to perform a garbage collection operation according to a first frequency when the programmed page ratio is less than a first threshold value (FIG. 6: step S622). Regarding dependent claim 3, Na teaches wherein determining the garbage collection policy comprises determining that the garbage collection operation is to be performed as a background operation of the semiconductor memory device (see 6:3-10). Regarding dependent claim 4, Na teaches wherein determining the garbage collection policy comprises determining to perform a garbage collection operation according to a second frequency higher than the first frequency when the programmed page ratio is equal to or greater than the first threshold value and less than or equal to the second threshold (FIG. 6: step S622, see 13:61-14:59). Regarding dependent claim 5, Na teaches wherein determining the garbage collection policy comprises determining to perform the garbage collection operation as a foreground operation of the semiconductor memory device when the programmed page ratio exceeds the second threshold value (see 9:10-17). Regarding dependent claim 6, Na teaches controlling the semiconductor memory device to perform a garbage collection operation, based on the determined garbage collection policy (see FIGS. 5-6). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. September 28, 2026 /VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
Read full office action

Prosecution Timeline

Jan 16, 2025
Application Filed
Oct 01, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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METHOD FOR EFFICIENTLY WAKING UP FERROELECTRIC MEMORY
2y 3m to grant Granted Oct 20, 2026
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TRANSCEIVER ARCHITECTURE WITH LOW KICK-BACK NOISE AND PAD CAP
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2y 2m to grant Granted Aug 04, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
89%
With Interview (+6.4%)
2y 2m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 968 resolved cases by this examiner. Grant probability derived from career allowance rate.

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