CTNF 19/025,909 CTNF 81768 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claim 20 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim does not fall within at least one of the four categories of patent eligible subject matter because the claim is directed to a signal per se and mere information in the form of data. More specifically, the claim is directed to a “computer storage medium encoded with instructions” (see line 1). However, the instant specification states at paragraph 0056 that a “computer storage medium” may be able to take the form of “an artificially-generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal”. Accordingly, the claim is directed to non-statutory subject matter. Applicant is advised to add the limitation “non-transitory” to the claim in order to overcome the present 35 USC § 101 rejection. See 1351 OG 212. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1, 3, 4, 10, 11, 13, 14, and 20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Winemiller et al. (U.S. Patent Application Publication Number 2017/0329386) . Regarding Claim 1 , Winemiller discloses a system (Figure 2, item 200) comprising: a stand-by clock (Figure 2, item 206, paragraph 0021), configured to produce a stand-by clock signal when the system is in a low-power mode (paragraph 0021; e.g., a U3 power state) and to produce a start-up signal when the system switches from the low-power mode to an active mode (paragraphs 0023, 0025, and claim 1; i.e., the edges of the low frequency clock signal 206 act as the start-up signal because they are used to provide the FLL enable signal 308); a primary clock (Figure 3, item 304, paragraph 0022), configured to produce a primary clock signal when the system is in the active mode (paragraph 0025 and claim 1; i.e., waking the system long enough to detect the LFPS signals, which could also result in the entire system entering the U0 state [either state of which could be equated to the claimed “active mode”]); and wherein the system is configured to switch from the low-power mode to the active mode by providing the start-up signal from the stand-by clock to the primary clock (paragraphs 0022, 0023, and 0025 and claim 8; i.e., the low frequency clock signal [stand-by clock signal 206] is used to provide the FLL enable signal 308, which causes the system to enter the active mode [e.g., waking the signal detection circuitry or entering the U0 state]). Regarding Claims 3 and 13 , Winemiller discloses wherein the stand-by clock produces the start-up signal using the stand-by clock signal (paragraph 0025). Regarding Claims 4 and 14 , Winemiller discloses wherein the start-up signal is the stand-by clock signal (paragraph 0025). Regarding Claim 10 , Winemiller discloses wherein the power required by the stand-by clock to produce the stand-by clock signal is less than the power required by the primary clock to produce the primary clock signal (paragraphs 0020 and 0022; i.e., a clock that operates at 32 kHz requires less power than a clock that operates at 20 MHz). Regarding Claim 11 , Winemiller discloses a method comprising: outputting a stand-by clock signal from a stand-by clock (Figure 2, item 206, paragraph 0021) when in a low-power mode (paragraph 0021; e.g., a U3 power state); outputting a primary clock signal from a primary clock (Figure 3, item 304, paragraph 0022) when in an active mode (paragraph 0025 and claim 1; i.e., waking the system long enough to detect the LFPS signals, which could also result in the entire system entering the U0 state [either state of which could be equated to the claimed “active mode”]); and transitioning from the low-power mode to the active mode by providing a start-up signal from the stand-by clock to the primary clock (paragraphs 0022, 0023, and 0025 and claim 8; i.e., the low frequency clock signal [stand-by clock signal 206] is used to provide the FLL enable signal 308, which causes the system to enter the active mode [e.g., waking the signal detection circuitry or entering the U0 state]). Regarding Claim 20 , Winemiller discloses a computer storage medium encoded with instructions that are operable, when executed by data processing apparatus (paragraph 0033), to cause the data processing apparatus to perform operations comprising: outputting a stand-by clock signal from a stand-by clock (Figure 2, item 206, paragraph 0021) when in a low-power mode (paragraph 0021; e.g., a U3 power state); outputting a primary clock signal from a primary clock (Figure 3, item 304, paragraph 0022) when in an active mode (paragraph 0025 and claim 1; i.e., waking the system long enough to detect the LFPS signals, which could also result in the entire system entering the U0 state [either state of which could be equated to the claimed “active mode”]); and transitioning from the low-power mode to the active mode by providing a start-up signal from the stand-by clock to the primary clock (paragraphs 0022, 0023, and 0025 and claim 8; i.e., the low frequency clock signal [stand-by clock signal 206] is used to provide the FLL enable signal 308, which causes the system to enter the active mode [e.g., waking the signal detection circuitry or entering the U0 state]) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 2, 6-9, 12, and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Winemiller as applied to Claims 1 and 11, and further in view of Carlton et al. (U.S. Patent Application Publication Number 2021/0305939) . Regarding Claims 2 and 12 , Winemiller discloses wherein the primary clock is configured to start up with or without the start-up signal from the stand-by clock (paragraph 0022; i.e., as long as the primary clock 304 receives the FLL enable signal 308, it can start up, which theoretically could occur without the stand-by clock 208). Winemiller does not expressly disclose wherein starting the primary clock using the start-up signal from the stand-by clock is faster than starting the primary clock without the start-up signal from the stand-by clock. In the same field of endeavor (e.g., clock control techniques), Carlton teaches wherein starting the primary clock (Figure 1, item 101) using the start-up signal from the stand-by clock (Figure 1, item 102) is faster than starting the primary clock without the start-up signal from the stand-by clock (paragraph 0030). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Carlton’s teachings of clock control techniques with the teachings of Winemiller, for the purpose of increasing the speed at which the primary clock starts up. Regarding Claims 6 and 16 , Carlton teaches wherein the primary clock comprises: a crystal resonator, wherein the crystal resonator has a fundamental resonant frequency (Figure 1, item 101a, paragraph 0028); and an oscillator circuit (Figure 1, item 101), configured to amplify signals from the crystal resonator and send signals to the crystal resonator (paragraph 0035). Regarding Claims 7 and 17 , Carlton teaches wherein using the start-up signal from the stand-by clock to start up comprises: receiving, by the oscillator circuit, the start-up signal from the stand-by clock (paragraph 0028); and sending the startup signal to the crystal resonator (paragraphs 0029-0030). Regarding Claims 8 and 18 , Carlton teaches wherein the particular resonant frequency of the primary clock is the fundamental resonant frequency of the crystal resonator (paragraph 0030). Regarding Claims 9 and 19 , Carlton teaches wherein the stand-by clock comprises: a linear oscillator circuit, configured to produce an oscillator signal (Figure 1, item 102); and a phase locked loop circuit (paragraph 0070) configured to: receive the oscillator signal from the linear oscillator circuit (paragraph 0028); and multiply the frequency of the oscillator signal to produce the start-up signal targeting the particular resonant frequency of the primary clock (paragraphs 0029-0030). Regarding Claim 15 , Carlton teaches wherein the start-up signal is based on a particular resonant frequency of the primary clock (paragraph 0030); and the primary clock is configured to use the start-up signal to start up (paragraph 0029) . 07-21-aia AIA Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Winemiller as applied to Claim 1, and further in view of Lai (U.S. Patent Application Publication Number 2019/0196563) and Carlton . Regarding Claim 5 , Winemiller does not expressly disclose a multiplexer configured to: receive the stand-by clock signal and the primary clock signal; output the stand-by clock signal when the system is in the low-power mode; and output the primary clock signal when the system is in the active mode; wherein: the start-up signal is based on a particular resonant frequency of the primary clock; and the primary clock is configured to use the start-up signal to start up. In the same field of endeavor (e.g., clock control techniques), Lai teaches a multiplexer (Figure 1, item 150) configured to: receive the stand-by clock signal (Figure 1, item 110) and the primary clock signal (Figure 1, items 120 and 130, paragraph 0017); output the stand-by clock signal when the system is in the low-power mode (paragraph 0020); and output the primary clock signal when the system is in the active mode (paragraph 0020). Accordingly it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Lai’s teachings of clock control techniques with the teachings of Winemiller, for the purpose of avoiding the need to have both clocks operate simultaneously when only one of the clocks is required for operation of the system. Also in the same field of endeavor (e.g., clock control techniques), Carlton teaches wherein the start-up signal is based on a particular resonant frequency of the primary clock (paragraph 0030); and the primary clock (Figure 1, item 101) is configured to use the start-up signal to start up (paragraph 0029). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Carlton’s teachings of clock control techniques with the teachings of Winemiller, for the purpose of increasing the speed at which the primary clock starts up . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses a system with a power conserving clock that is used for fast startup . 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175 Application/Control Number: 19/025,909 Page 2 Art Unit: 2175 Application/Control Number: 19/025,909 Page 3 Art Unit: 2175 Application/Control Number: 19/025,909 Page 4 Art Unit: 2175 Application/Control Number: 19/025,909 Page 5 Art Unit: 2175 Application/Control Number: 19/025,909 Page 6 Art Unit: 2175 Application/Control Number: 19/025,909 Page 7 Art Unit: 2175 Application/Control Number: 19/025,909 Page 8 Art Unit: 2175 Application/Control Number: 19/025,909 Page 9 Art Unit: 2175 Application/Control Number: 19/025,909 Page 10 Art Unit: 2175