DETAIL ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. The instant application having application No. 19/027,352 has a total of 20 claims pending in the application; there are 3 independent claim and 17 dependent claims, all of which are ready for examination by the examiner..
IFORMATION CONCENING DRAWING:
3. Application’s drawing submitted on 01/17/2025 are acceptable for examination purposes.
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
Information Disclosure Statement
4. As required by M.P.E.P. 2001.06(b) and 37 C.F.R. 1.98(d), since the instant application has been identified as a continuation application of an earlier filed application and is relied upon for an earlier filing date under 35 U.S.C. 120, the examiner has reviewed the prior art cited in the earlier related application as required by M.P.E.P. 707.05 and 904 and as stated in M.P.E.P. 2001.06(b), no separate citation of the same prior art need be made by the applicants in the instant application.
INFORMATION CONCERNING IDS:
5. The information disclosure statement (IDS) submitted on 02/06/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the Examiner.
IFORMATION CONCENING CLAIMS:
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
6. Claim 1-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of copending Application No. 18/363,438 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because claims of reference application recite limitation(s) that are not expressly recited in the claim(s) of instant Application.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
7. Claims 1-20 of the current is compared to claims 1-20 of the co-pending Application No. 18/363,438 (reference application), filed 10/15/2025 in the following table:
US Application 19/027,352
US Application 18/363,438
1. A system, comprising: a memory configurable as a plurality of stacks;
a controller operable to: measure usages of the stacks; and
adjust how the memory is partitioned for allocation to the plurality of stacks.
1. A system, comprising: a memory configurable as a plurality of stacks;
wherein each of the plurality of stacks comprises a portion of memory and is assigned to a processor or process; and
a controller operable to: measure usages of the stacks; and
adjust, based on the usages, how the memory is partitioned for allocation of each processor or process to its assigned one of the plurality of stacks.
2. The system of claim 1, further comprising:
a set of media, wherein the controller is further operable to control operations to access the set of media using the plurality of stacks.
2. (Original) The system of claim 1, further comprising:
a set of media, wherein the controller is further operable to control operations to access the set of media using the plurality of stacks.
3. The system of claim 2,
wherein the set of media includes a flash memory.
3. (Original) The system of claim 2,
wherein the set of media includes a flash memory.
4. The system of claim 3,
wherein the system is configured as a solid state drive.
4. (Original) The system of claim 3,
wherein the system is configured as a solid state drive.
5. The system of claim 4,
wherein the controller is operable to operate the stacks in executing commands received in the solid state drive to: store data in the flash memory; and retrieve data from the flash memory.
5. (Original) The system of claim 4
wherein the controller is operable to operate the stacks in executing commands received in the solid state drive to: store data in the flash memory; and retrieve data from the flash memory.
6. The system of claim 5,
wherein the controller is further operable to: fill unused portions of the memory with a predetermined value pattern; and
search for boundaries of the stacks based on the predetermined value pattern;
wherein the usages of the stacks are measured based on the boundaries.
6. (Original) The system of claim 5,
wherein the controller is further operable to: fill unused portions of the memory with a predetermined value pattern; and
search for boundaries of the stacks based on the predetermined value pattern,
wherein the usages of the stacks are measured based on the boundaries.
7. The system of claim 6, wherein the predetermined value pattern is a predetermined value.
7. (Original) The system of claim 6,
wherein the predetermined value pattern is a predetermined value.
8. The system of claim 6,
wherein the predetermined value pattern includes a predetermined relation between a location in the memory and a value stored at the location in the memory.
8. (Original) The system of claim 6,
wherein the predetermined value pattern includes a predetermined relation a location in the memory and a value stored at the location in the memory.
9. The system of claim 6,
wherein the controller is operable to search the boundaries by: identifying, in the memory, a region containing a boundary between a portion having the predetermined value pattern and a portion not having the predetermined value pattern;
retrieving a value from a location within the region, wherein the location divides the region into a first region and a second region;
determining whether the value agrees with the predetermined value pattern; and
identifying, based on whether the value agrees with the predetermined value pattern, either the first region or the second region as a region containing the boundary.
9. The system of claim 6,
wherein the controller is operable to search the boundaries by: identifying, in the memory, a region containing a boundary between a portion having the predetermined value pattern and a portion not having the predetermined value pattern;
retrieving a value from a location within the region, wherein the location divides the region into a first region and a second region;
determining whether the value agrees with the predetermined value pattern; and
identifying, based on whether the value agrees with the predetermined value pattern, either the first region or the second region as a region containing the boundary.
10. A method, comprising: partitioning a memory into a plurality of segments; operating a plurality of stacks in the plurality of segments respectively;
measuring usages of the stacks during a period of time; and
adjusting partition of the plurality of segments in the memory for the plurality of stacks.
10. A method, comprising: partitioning a memory into a plurality of segments; operating a plurality of stacks in the plurality of segments respectively; wherein each of the plurality of stacks is assigned to a processor, processing core, or process;
measuring usages of the stacks during a period of time; and
adjusting, based on the measured usages, partition of the plurality of segments in the memory of each processor or process for its assigned one of the plurality of stacks.
11. The method of claim 10, further comprising:
executing commands to access a set of media based on operating the stacks.
11. (Original) The method of claim 10, further comprising:
executing commands to access a set of media based on operating the stacks.
12. The method of claim 11,
wherein the commands are configured to store data into the set of media and to retrieve data from the set of media.
12. (Original) The method of claim 11, wherein the commands are configured to store data into the set of media and to retrieve data from the set of media.
13. The method of claim 10, further comprising:
filling unused portions of the memory with a predetermined value pattern; and searching for a boundary of a stack and an unused portion of the memory based on the predetermined value pattern.
13. (Original) The method of claim 10, further comprising:
filling unused portions of the memory with a predetermined value pattern; and searching for a boundary of a stack and an unused portion of the memory based on the predetermined value pattern.
14. The method of claim 13,
wherein the predetermined value pattern is represented by a predetermined value.
14. (Original) The method of claim 13, wherein the predetermined value pattern is represented by a predetermined value.
15. The method of claim 13,
wherein the predetermined value pattern includes a predetermined relation between a location in the memory and a value stored at the location.
15. (Original) The method of claim 13,
wherein the predetermined value pattern includes a predetermined relation between a location in the memory and a value stored at the location.
16. The method of claim 13,
wherein the searching includes:
identifying, in the memory, a region containing the boundary between the unused portion having the predetermined value pattern and a portion not having the predetermined value pattern; retrieving a value from a location within the region, wherein the location divides the region into a first region and a second region;
determining whether the value agrees with the predetermined value pattern; and
identifying, based on whether the value agrees with the predetermined value pattern, either the first region or the second region as a region containing the boundary.
16. (Original) The method of claim 13, wherein the searching includes: identifying, in the memory, a region containing the boundary between the unused portion having the predetermined value pattern and a portion not having the predetermined value pattern; retrieving a value from a location within the region, wherein the location divides the region into a first region and a second region;
determining whether the value agrees with the predetermined value pattern; and
identifying, based on whether the value agrees with the predetermined value pattern, either the first region or the second region as a region containing the boundary.
17. A non-transitory computer storage medium storing instructions which when executed by a controller cause the controller to perform a method, the method comprising:
partitioning a memory into a plurality of segments;
operating a plurality of stacks in the plurality of segments respectively;
measuring usages of the stacks during a period of time; and
adjusting partition of the plurality of segments in the memory for the plurality of stacks.
17. (Currently Amended) A non-transitory computer storage medium storing instructions which when executed by a controller cause the controller to perform a method, the method comprising:
partitioning a memory into a plurality of segments;
operating a plurality of stacks in the plurality of segments respectively, wherein each of the plurality of stacks comprises a portion of the memory and is assigned to a processor or process; measuring usages of the stacks during a period of time; and
adjusting, based on the measured usages, partition of the plurality of segments in the memory of each processor or process for its assigned one of the plurality of stacks.
18. The non-transitory computer storage medium of claim 17,
wherein the measuring of the usages comprises: filling unused portions of the memory with a predetermined value pattern; and
searching for a boundary of a stack and an unused portion of the memory based on the predetermined value pattern.
18. (Original) The non-transitory computer storage medium of claim 17, wherein the measuring of the usages comprises: filling unused portions of the memory with a predetermined value pattern; and
searching for a boundary of a stack and an unused portion of the memory based on the predetermined value pattern.
19. The non-transitory computer storage medium of claim 18, wherein the searching for the boundary comprises:
identifying, in the memory, a region containing the boundary between the unused portion having the predetermined value pattern and a portion not having the predetermined value pattern;
retrieving a value from a location within the region, wherein the location divides the region into a first region and a second region;
determining whether the value agrees with the predetermined value pattern; and
identifying, based on whether the value agrees with the predetermined value pattern, either the first region or the second region as a region containing the boundary.
19. (Original) The non-transitory computer storage medium of claim 18, wherein the searching for the boundary comprises:
identifying, in the memory, a region containing the boundary between the unused portion having the predetermined value pattern and a portion not having the predetermined value pattern;
retrieving a value from a location within the region, wherein the location divides the region into a first region and a second region;
determining whether the value agrees with the predetermined value pattern; and
identifying, based on whether the value agrees with the predetermined value pattern, either the first region or the second region as a region containing the boundary.
20. (Original) The non-transitory computer storage medium of claim 18,
wherein the predetermined value pattern includes a predetermined relation between a location in the memory and a value stored at the location.
20. (Original) The non-transitory computer storage medium of claim 18, wherein the predetermined value pattern includes a predetermined relation between a location in the memory and a value stored at the location.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 10, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Shearer “Shearer” (US 2005/0076166 A1) in view of Edrich “Edrich” (US 2004/0260917 A1) .
8. Regarding claim 1, Shearer teaches or suggests:
“a system [e.g., Fig. 2], comprising: a memory configurable as a plurality of stacks; [e.g., Fig. 3 and ¶ 0026 shows a controller 204 and buffer memory 206 (a stack memory) partitioned into a plurality of virtual lane regions (i.e. divided into a plurality of stacks)]
“and a controller (e.g., memory controller 204 in Figs. 2-4) operable to: measure usages of the stacks;” [e.g., ¶ 0027, What is important is that some indicia of virtual lane buffer region usage is used so that the dimensions of the virtual lane buffer regions can be adjusted to improve system operation; ¶ 0028).
“adjust how the memory is partitioned for allocation to the plurality of stacks” [Figs. 3, 4, and ¶ 0028 show that in response to the measured usage, the buffer is repartitioned (i.e. the partitioning of the stack memory into the plurality of stacks is adjusted)]. However, Shearer does not appear to expressly teach while Edrich discloses:
“wherein each of the plurality of stacks is assigned to a processor or process;” (e.g., ¶ 0039, For example, each processor may be assigned its own stack memory) assigning to each processor of a plurality of processors its own stack memory.
Disclosures by Shearer and Edrich are analogous because they are in the same field of endeavor and/or solving a similar or common problem.
It would have been obvious to a person of having ordinary skill in the art before the effective filing date of the claimed invention to modify the controlled buffer regions taught by Shearer to include the assignment of stacks disclosed by Edrich.
The motivation for including the assignment of stacks as taught by paragraph [0039] of Edrich is to avoid conflict. In addition, interrupts may be disabled for all of the processors involved in the MP kernel (other than the BSP) to avoid multiple processors interacting with the programmable interrupt controller at the same time.
Therefore, it would have been obvious to combine teaching of Edrich with Shearer to obtain the invention as specified in the claim.
9. Claims 10 and 17 are similarly rejected by Shearer in view of Edrich. Claims 10 and 17 present method and non- transitory computer readable media claims (respectively) covering the same subject matter as claim 1. As such, Shearer in view of Edrich teach or render obvious each and every limitation of claims 10 and 17 in the same manner as claim 1; as the minor differences in claim language are fully taught as presented in the rejection above.
Claims 2-5 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Shearer in view of Edrich as applied to claims 1 and 10 above, and further in view of WORLEY et al. “Worley” (US 2016/0259597 A1).
10. Regarding claim 2 and 11, taking claim 2 as exemplary, Shearer in view of Edrich teach all limitations recited in claims 1 and 10 but do not expressly teach while Worley discloses:
Worley discloses: “a set of media, wherein the controller is further operable to control operations to access the set of media using the plurality of stacks.” [e.g., Fig. 3 and ¶ 0049 teaches a storage drive which utilizes a volatile flash memory to cache received data during protocol identification/translation, showing volatile memory 345 (the stack memory) and mixed-format media set 355 (a set of media). See also Fig. 10A-B and 0081- 0082 that further demonstrate that the memory 345 is used for caching of data for transmission to/from the mixed media set, where Shearer's memory is arranged as a plurality of stacks as demonstrated above. (i.e. the controller accesses the set of media using the plurality of stacks)]
Disclosures by Shearer, Edrich and Worley are analogous because they are in the same field of endeavor and/or solving a similar or common problem.
It would have been obvious to a person of having ordinary skill in the art before the effective filing date of the claimed invention to modify the controlled buffer regions taught by Shearer to include the assignment of stacks disclosed by Edrich; furthermore, to include volatile memory as stacks to access one or more mixed-format mixed-protocol non-volatile memory units taught by Worley.
The motivation for including the assignment of stacks as taught by paragraph [0039] of Edrich is to avoid conflict. In addition, interrupts may be disabled for all of the processors involved in the MP kernel (other than the BSP) to avoid multiple processors interacting with the programmable interrupt controller at the same time; furthermore, the motivation to include to include volatile memory (e.g., as stacks) to control access to set of non-volatile memories as taught by paragraph [0031] of Worley includes ability to support multiple types of memory and/or storage, which in turn improves system performance.
Therefore, it would have been obvious to combine teachings of Worley and Edrich with Shearer to obtain the invention as specified in the claim.
11. Regarding claim 3, Worley further teaches:
“wherein the set of media includes a flash memory.” [e.g., Fig. 3, ¶ 0046 shows that the media 355 is mixed-format SSD (flash) units.] The reasons for obviousness are the same as those applied for claim 2 above.
12. Regarding claim 4, Worley further teaches:
“wherein the system is configured as a solid state drive.” [e.g., Fig. 3 and ¶ 0046 shows that the media 355 is mixed-format SSD (flash) units.] The reasons for obviousness are the same as those applied for claim 2 above.
13. Regarding claim 5, Worley further teaches:
“wherein the controller is operable to operate the stacks in executing commands received in the solid state drive to: store data in the flash memory; and retrieve data from the flash memory.” [e.g., Fig. 3 and ¶ 0049 shows that the memory 345 is utilized as a cache to interface with the set of media.]
14. Claim 12 presents the same subject matter as claim 5, dependent from claim 11 rather than claim 4. As such, Shearer and Worley teach the limitations of claim 12 in the same manner.
Claims 6-8 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Shearer in view of Edrich and Worley as applied to claims 5 and 10 (respectively) above, and further in view of Park et al. (US 2014/0359246 A1).
15. Regarding claim 6 Shearer, Edrich, and Worley teach all limitations included in claim 5 but do not teach while Park discloses:
“wherein the controller is further operable to: fill unused portions of the memory with a predetermined value pattern;” [Park Fig. 1, 2 and ¶¶ 0022-0023 teaches that all unused space in stack regions are initialized with the initial default value (i.e. the controller fills them with the predetermined value)]
and search for boundaries of the stacks based on the predetermined value pattern, wherein the usages of the stacks are measured based on the boundaries.” [e.g., Fig. 1 and 2 show that the blocks of the stack are searched to determine the boundary location between used and unused data to determine the current stack size (i.e. the usage). See [0037]-[0040] which discloses a detailed example of how this is performed.]
Disclosures by Shearer, Edrich, Worley, and Park are analogous because they are in the same field of endeavor and/or solving a similar or common problem.
It would have been obvious to a person of having ordinary skill in the art before the effective filing date of the claimed invention to modify the controlled buffer regions taught by Shearer to include the assignment of stacks disclosed by Edrich; furthermore, to include volatile memory as stacks to access one or more mixed-format mixed-protocol non-volatile memory units taught by Worley; furthermore, to include monitoring/determining stack size and/or boundary taught by Park.
The motivation for including the assignment of stacks as taught by paragraph [0039] of Edrich is to avoid conflict. In addition, interrupts may be disabled for all of the processors involved in the MP kernel (other than the BSP) to avoid multiple processors interacting with the programmable interrupt controller at the same time; furthermore, the motivation to include to include volatile memory (e.g., as stacks) to control access to set of non-volatile memories as taught by paragraph [0031] of Worley includes ability to support multiple types of memory and/or storage, which in turn improves system performance; furthermore, the motivation to include the monitoring/determining stack size and/or boundary as taught by paragraph [0011] of Park is that, when the control system reaches a risk level of stack overflow, fail-safe logic is entered and an overflow phenomenon of the memory stack can be easily prevented.
Therefore, it would have been obvious to combine teachings of Park, Worley and Edrich with Shearer to obtain the invention as specified in the claim.
16. Claim 13 present the same subject matter as claim 6, dependent from claim 10 rather than claim 5. As such, Shearer, Worley, and Park teach the limitations of claim 13 in the same manner.
17. Regarding Claim 7, Park further teaches:
“wherein the predetermined value pattern is a predetermined value.” [e.g., ¶ [0022] teaches that the predetermined value pattern is the value 0xFFFFFFFF].
18. Claim 14 presents the same subject matter as claim 7, dependent from claim 13 rather than claim 6. As such, Shearer, Worley, and Park teach the limitations of claim 14 in the same manner.
19. Regarding Claim 8, Park further teaches:
“wherein the predetermined value pattern includes a predetermined relation a location in the memory and a value stored at the location in the memory.” [e.g., ¶ [0022] teaches that the value is stored in all locations that are not in use (i.e. having the predetermined relation with the location)]
20. Claim 15 presents the same subject matter as claim 8, dependent from claim 13 rather than claim 6. As such, Shearer, Worley, and Park teach the limitations of claims 15 in the same manner.
Claims 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Shearer in view of Edrich, as applied to claim 17 above, and further in view Park.
21. Regarding claim 18, Shearer in view of Edrich teach all limitation recited in claim 17 but do not expressly teach while Park discloses:
“wherein the measuring of the usages comprises: filling unused portions of the memory with a predetermined value pattern;” [Park: Fig. 1, 2 and ¶¶ 0022-0023] teaches that all unused space in stack regions are initialized with the initial default value (i.e. the controller fills them with the predetermined value)]
“and searching for a boundary of a stack and an unused portion of the memory based on the predetermined value pattern.” [Park: Fig. 1 and 2 show that the blocks of the stack are searched to determine the boundary location between used and unused data to determine the current stack size (i.e. the usage). See [0037]-[0040] which discloses a detailed example of how this is performed.]
Disclosures by Shearer, Edrich, and Park are analogous because they are in the same field of endeavor and/or solving a similar or common problem.
It would have been obvious to a person of having ordinary skill in the art before the effective filing date of the claimed invention to modify the controlled buffer regions taught by Shearer to include the assignment of stacks disclosed by Edrich; furthermore, to include monitoring/determining stack size and/or boundary taught by Park.
The motivation for including the assignment of stacks as taught by paragraph [0039] of Edrich is to avoid conflict. In addition, interrupts may be disabled for all of the processors involved in the MP kernel (other than the BSP) to avoid multiple processors interacting with the programmable interrupt controller at the same time; furthermore, the motivation to include the monitoring/determining stack size and/or boundary as taught by paragraph [0011] of Park is that, when the control system reaches a risk level of stack overflow, fail-safe logic is entered and an overflow phenomenon of the memory stack can be easily prevented.
Therefore, it would have been obvious to combine teachings of Park and Edrich with Shearer to obtain the invention as specified in the claim.
22. Regarding Claim 20, Park further teaches:
“wherein the predetermined value pattern includes a predetermined relation between a location in the memory and a value stored at the location.” [e.g., ¶ [0022] teaches that the value is stored in all locations that are not in use (i.e. having the predetermined relation with the location)] The reasons for obviousness for claim 20 is the same as that presented for claim 18 above.
Conclusion
the prior art made of record and not relied upon are as follows:
1. Jackson (US 20150205612 A1) teaches “…processors dynamically allocate memory, there may be data added to the stack (resulting in a change in the stack pointer) as a result of the dynamic allocation…” (par. 0150).
2. GROSSI et. al (US 20150150024 A1) teaches “ …studying the values of SPMin and SPMax at the end of the various processes makes it possible to optimize the allocation of memory for the stacks” (par. 0047).
3. YI (US 20130055282 A1) teaches “…However, average response time, scheduling latency, and primitivity are much poorer than that of the multithreaded system [17]. The design of the multi-threaded provides fully-preemptible task management. But necessary memory space is much larger than the event-driven system because each thread requires its own stack space (par. 0034).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HASHEM FARROKH whose telephone number is (571)272-4193. The examiner can normally be reached Monday through Friday from 8:30 am - 5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Mr. Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see htto://pair-direct.uspto.gov. For questions regarding access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786- 9199 (IN USA OR CANADA) or 571-272-1000.
/HASHEM FARROKH/ Primary Examiner, Art Unit 2138