Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1-20 are pending.
Claim Rejections - 35 USC § 103
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Komatsu (US Patent Application Publication 2007/0061648) in view of Kim et al. (US Patent 11,127,364), herein after referred to as Kim.
Regarding independent claim 1, Komatsu discloses a display device (Figure 1 and paragraph [0028] describes a display.) comprising:
a controller configured to generate a start signal (SP) and a clock signal (CLK) (Figure 3 clock control circuit CCCn described in paragraphs [0031]-[0032] to control and output clock signals CLK. Figure 2 and paragraph [0029] describes the shift circuit block SB1 to receive a start pulse SP and inverted SP via 50. Figure 5 depicts CCCn to output CLK via a received input of CLK. The wires which outputs SP and CLK are inherently generated and therefore interpreted to regard the claimed controller.);
a masking circuit (CCCn) configured to generate output clock signals (CLK and
C
L
K
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) by masking at least a portion of the clock signal (The current application’s originally filed specification paragraph [00113] examples masking as refraining from driving the first and second stage in particular periods of the shifter register. Prior art Komatsu figures 5-6 and paragraphs [0032] and [0040] describes when the NAND is turned to a lower level the control circuit CCCn “stops supplying”/masking the clock signal CLKn.); and
a plurality of stages (SU) configured to receive an output clock signal (CLK and
C
L
K
-
) of the output clock signals (CLK and
C
L
K
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) in response to the start signal (SP) and output a data signal (Q2m) (Figure 3 reference shift unit circuits SU to receive start pulse SP and clock signals CLK as described in paragraphs [0029]-[0031]. Paragraph [0032] describes the output of SU to NAND regarding Q2m.),
wherein the masking circuit (CCCn) is configured to receive data signals (Q2m) respectively output from a stage (SU2m(n-1)+2) of the plurality of stages (SU) and at least one other stage (SU2m(n-1)+4) disposed [ ] adjacent to the stage (Paragraph [0032] describes the NAND input of Q2m to be successively adjacent even numbered shift register stages SU.).
Komatsu does not specifically disclose the at least one other stage to be disposed directly adjacent to the stage.
Kim discloses odd and even shift register stages to be respectively disposed on the left and right sides of the display such that the even numbered shifter register stages ST2, ST4 …ST(2) are each respectively directly disposed adjacent to each other in sequence (figures 2 and 4 depicts ST2 directly adjacent to ST4).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Komatsu’s even and odd shift registers with the known technique of being disposed on respect sides of the display such that the even shift register stage (ST2) is disposed directly adjacent to the at least one other stage (ST4) yielding the predictable results of reducing bezel width as disclosed by Kim (Column 14 line 60 to column 15 line 17).
Regarding claim 2, Komatsu discloses the display device of claim 1, wherein the plurality of stages comprise a first stage (Figure 3 SU2m(n-1)+2) and a second stage (SU2m(n-1)+4) following the first stage (Paragraph [0032] describes the NAND input of Q2m to be successively adjacent even numbered shift register stages SU.), and
wherein the masking circuit (CCCn) comprises a first masking circuit configured to receive the start signal (Figure 2 inverter 50), a first data signal (Q2m(n-1)+2) output from the first stage (SU2m(n-1)+2), and a second data signal (Q2m(n-1)+4) output from the second stage (SU2m(n-1)+2).
Regarding independent claim 20, Komatsu discloses an electronic device (Figure 1 and paragraph [0028] describes a display.) comprising:
a display device(Figure 1 and paragraph [0028] describes a display.) configured to display an image based on input image data (pixels 31 paragraph [0028]); and
a processor configured to provide the input image data to the display device (Figure 1 DATA to data latch 12 paragraph [0028]),
wherein the display device comprises:
a controller configured to generate a start signal (SP) and a clock signal (CLK) (Figure 3 clock control circuit CCCn described in paragraphs [0031]-[0032] to control and output clock signals CLK. Figure 2 and paragraph [0029] describes the shift circuit block SB1 to receive a start pulse SP and inverted SP via 50. Figure 5 depicts CCCn to output CLK via a received input of CLK. The wires which outputs SP and CLK are inherently generated and therefore interpreted to regard the claimed controller.);
a masking circuit (CCCn) configured to generate output clock signals (CLK and
C
L
K
-
) by masking at least a portion of the clock signal (The current application’s originally filed specification paragraph [00113] examples masking as refraining from driving the first and second stage in particular periods of the shifter register. Prior art Komatsu figures 5-6 and paragraphs [0032] and [0040] describes when the NAND is turned to a lower level the control circuit CCCn “stops supplying”/masking the clock signal CLKn.); and
a plurality of stages (SU) configured to receive an output clock signal (CLK and
C
L
K
-
) of the output clock signals (CLK and
C
L
K
-
) in response to the start signal (SP) and output a data signal (Q2m) (Figure 3 reference shift unit circuits SU to receive start pulse SP and clock signals CLK as described in paragraphs [0029]-[0031]. Paragraph [0032] describes the output of SU to NAND regarding Q2m.),
wherein the masking circuit (CCCn) is configured to receive data signals (Q2m) respectively output from a stage (SU2m(n-1)+2) of the plurality of stages (SU) and at least one other stage (SU2m(n-1)+4) disposed [ ] adjacent to the stage (Paragraph [0032] describes the NAND input of Q2m to be successively adjacent even numbered shift register stages SU.).
Komatsu does not specifically disclose the at least one other stage to be disposed directly adjacent to the stage.
Kim discloses odd and even shift register stages to be respectively disposed on the left and right sides of the display such that the even numbered shifter register stages ST2, ST4 …ST(2) are each respectively directly disposed adjacent to each other in sequence (figures 2 and 4 depicts ST2 directly adjacent to ST4).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Komatsu’s even and odd shift registers with the known technique of being disposed on respect sides of the display such that the even shift register stage (ST2) is disposed directly adjacent to the at least one other stage (ST4) yielding the predictable results of reducing bezel width as disclosed by Kim (Column 14 line 60 to column 15 line 17).
Allowable Subject Matter
4. Claims 3-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, Komatsu does not specifically disclose wherein the first masking circuit (50) is configured to supply a first output clock signal to the first stage, and supply a second output clock signal different from the first output clock signal to the second stage. Please note the objection to allowance relies upon the incorporation of claim 2 and claim 3 together.
Regarding claim 8, Komatsu discloses the display device of claim 1, wherein the plurality of stages comprise an i-th stage (Figure 3 SU2m(n-1)+2), an (i−1)th stage (SU2m(n-1)+1) preceding the i-th stage (SU2m(n-1)+2), and an (i+1)th stage (SU2m(n-1)+3) following the i-th stage (SU2m(n-1)+2). However, Komatsu does not disclose a plurality of masking circuits including: wherein the masking circuit comprises an i-th masking circuit (CC) configured to receive an (i−1)th data signal output from the (i−1)th stage, an i-th data signal output from the i-th stage, and an (i+1)th data signal output from the (i+1)th stage.
Regarding claim 12, Komatsu discloses the display device of claim 1, wherein the plurality of stages comprise an (n−1)th stage (Figure 3 SU2m(n-1)+1) and an n-th stage (SU2m(n-1)+2) following the (n−1)th stage (SU2m(n-1)+1). However, Komatsu does not disclose a plurality of masking circuits including: wherein the masking circuit comprises an n-th masking circuit configured to receive the start signal, an (n−1)th data signal output from the (n−1)th stage, and an n-th data signal output from the n-th stage.
Regarding claim 15, Komatsu discloses the display device of claim 1, wherein the masking circuit (Figures 3 and 10 CCCn) comprises:
a logic operation unit (Figure 3 NAND) configured to receive an (i−1)th data signal (Q2m(n-1)+2), an i-th data signal (Q2m(n-1)+4), and an (i+1)th data signal (Q2m);
a first inverter (Figure 5 61a) comprising an input terminal (southern end of 61 as oriented in the figure) connected to a first node (REFn);
a first transistor (62/63) comprising an electrode configured to receive a voltage (VSS/VDD) from a first power source, [ ], and a gate electrode configured to receive a reset signal (REFn); an
N-type second transistor (64/65) comprising an electrode connected to a third node configured to receive the clock signal (CLK and
C
L
K
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), another electrode connected to a fourth node (output of CCCn), and a gate electrode connected to an output terminal of the first inverter (61a); and
a P-type third transistor (65/64) comprising an electrode connected to the third node (CLK and
C
L
K
-
), another electrode connected to the fourth node (output of CCCn), and a gate electrode connected to the first node (Inherently figure 10 utilizes the same type of transistor be it p or n for switches 64 and 65 to both receive the inverted signal 61a.).
However, Komatsu does not specifically disclose the first transistor another electrode connected to an output terminal of the logic operation unit. Please note it is the entirety of the language of claim 15 which enables the subject matter to be objected to allowance. Adding only the above line is not currently deemed allowable pending further search.
Cited but not relied upon:
Song et al. (US Patent Application Publication 2022/0328008) discloses masking circuits MS11, MS12, MS21, and MS22 in figure 10 but they are not arranged as claimed in claim 3.
Seo et al. (US Patent Application Publication 2021/0256912) describes a timing controller 10 (figure 1) can mask clock signals but they are not arranged as claimed in claim 3.
Response to Arguments
5. Applicant's arguments filed 5/4/2026 have been fully considered but they relate to newly amended subject matter. Newly cited art Kim is utilized in combination with previously cited art to reject the newly amended subject matter. Please refer to the above new rejection, necessitated by amendment, as the rebuttal. This action is final necessitated by amendment.
Conclusion
6. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER E LEIBY whose telephone number is (571)270-3142. The examiner can normally be reached 11-7.
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/CHRISTOPHER E LEIBY/Primary Examiner, Art Unit 2621
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