DETAILED ACTION
Response to Amendment
This action is responsive to the amendment filed on 6/18/2026. Claims 1-20 are pending and have been examined. Claims 1-5, 9 and 17-18 have been amended.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
The terminal disclaimer filed on 6/18/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of USPAT No. 12,265,827 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., abstract idea) without significantly more.
Regarding claim 1:
Subject Matter Eligibility Analysis Step 1:
Claim 1 recites “A device” and thus a machine, one of the four statutory categories of patentable subject matter.
Subject Matter Eligibility Analysis Step 2A Prong 1:
Claim 1 recites “…form a fifth value by appending the third value to the first value; form a sixth value by appending the fourth value to the second value… [[based on the first bit]] extend the fifth value to form a first extended value; [[based on the first bit]] extend the sixth value to form a second extended value…” which describe a process that under its broadest reasonable interpretation encompasses mathematical relationships and/or mental processes. That is other than reciting generic computing components (e.g. functional circuit, instruction decoder circuit …) nothing in the claimed elements precludes the steps from practically being performed in the mind and/or with the aid of pen and paper.
For example, the claim discusses forming values by appending values to other values (e.g. concatenating or combining values using elements 2102-2102 of Fig. 21) and extending the appended values by sign extension hardware (elements 2111-2112), thus the limitation encompasses mathematical relationships and/or mental processes (e.g. data manipulation) (MPEP 2106.04(a)(2)(I)(A)(iv) and (III)).
If a claim, limitation, under its broadest reasonable interpretation, covers performance of a mathematical relationship/mental process in the mind with the aid of pen and paper but for the recitation of generic computer components then it falls within the “Mathematical concepts” and/or “Mental Process” grouping of abstract ideas.
Subject Matter Eligibility Analysis Step 2A Prong 2:
Claim 1 further recites additional elements of
… a functional circuit; and an instruction decoder circuit coupled to the functional circuit… a first instruction specifying a first value, second value and a first bit…second instruction specifying a third value…a third instruction specifying a fourth value…. based on a first bit…based on the first bit…the functional circuit for performing an operation
…configurable to: receive a first instruction…receive a second instruction…receive a third instruction...provide the first extended value and the second extended value
These additional elements do not integrate the abstract idea into a practical application because (a) recites at a high-level of generality the words “apply it” (or an equivalent) with the judicial exception, or use mere instructions to implement the abstract idea on a computer, or merely uses a computer as a tool to perform the abstract idea (See MPEP 2106.05(f)) and (b) recites insignificant extra-solution activity (i.e. data gathering/outputting) (See MPEP 2106.05 (g)).
Therefore, claim 1 is directed to the abstract idea.
Subject Matter Eligibility Analysis Step 2B:
The additional elements of claim 1 do not provide significantly more than the abstract idea itself, taken alone and in combination, because (a) uses mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)); (b) recites insignificant extra-solution activity of data gathering/outputting (See MPEP 2106.05 (g)). Furthermore, (b) recites limitations which the courts have deemed to be well-understood, routine and conventional activities that do not provide significantly more (MPEP 2106.05(d)); the courts have recognized that receiving or transmitting data over a network ((Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362), as well as storing and retrieving information in memory are well‐understood, routine, and conventional functionalities (Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93)).
Therefore, based on the discussion of the additional elements above, claim 1 is not patent eligible.
Claim 2, dependent upon claim 1, further recites “…wherein to extend the fifth value, the instruction decoder circuit is configurable to sign extend the fifth value to form the first extended value based on the first bit”, which recites details of the abstract ideas (extension and sign extension) performed. The additional limitations tie the abstract idea to using mere instructions to implement an abstract idea on a computer or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 3, dependent upon claim 2, further recites “…wherein to extend the sixth value, the instruction decoder circuit is configurable to sign extend the sixth value to form the second extended value based on the first bit”, which recites details of the abstract ideas (extension and sign extension) performed. The additional limitations tie the abstract idea to using mere instructions to implement an abstract idea on a computer or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 4, dependent upon claim 1, further recites “…wherein the instruction decoder circuit is configurable to extend the fifth value to form the first extended value based on the first bit and based on a data size”, which recites details of the abstract ideas (extension) performed. The additional limitations tie the abstract idea to using mere instructions to implement an abstract idea on a computer or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 5, dependent upon claim 4, further recites “…wherein the instruction decoder circuit is configurable to extend the sixth value to form the second extended value based on the first bit and based on the data size”, which recites details of the abstract ideas (extension) performed. The additional limitations tie the abstract idea to using mere instructions to implement an abstract idea on a computer or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 6, dependent upon claim 1, further recites “…wherein the first bit indicates whether the first instruction is a scalar instruction or a vector instruction”, which recites details of particular data types (scalar or vector). The additional limitations tie the abstract idea to a particular data type, e.g. particular field of use or technological field to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(h)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 7, dependent upon claim 1, further recites “…wherein the operation is specified in the first instruction”. The additional limitations tie the abstract idea to using mere instructions to implement an abstract idea on a computer or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 8, dependent upon claim 1, further recites “…wherein the first instruction is adjacent to the second instruction in a packet”. The additional limitations tie the abstract idea to using mere instructions to implement an abstract idea on a computer or merely uses a computer as a tool to perform an abstract idea which cannot provide significantly more (see MPEP 2106.05(f)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claim 9, dependent upon claim 1, further recites “…wherein the instruction decoder circuit is configurable to receive a packet including the first instruction, the second instruction, and the third instruction, wherein the first instruction is adjacent to the second instruction in the packet, and wherein the second instruction is adjacent to the third instruction in the packet”. The additional limitations tie the abstract idea to using mere instructions to implement an abstract idea on a computer or merely uses a computer as a tool to perform an abstract idea and recite insignificant extra-solution activity of data gathering (which are well-understood, routine and conventional activities) which cannot provide significantly more (see MPEP 2106.05(d and f-g)). Therefore, the claim recites no additional elements which could integrate the abstract idea into a practical application nor provide significantly more than the abstract idea itself.
Claims 10-16 are similarly rejected on the same basis as claims 1-6 and 9 above.
Claims 17-20 are similarly rejected on the same basis as claims 3-5 and 8.
Allowable Subject Matter
Claims 1-20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 101, set forth in this Office action.
Response to Arguments
Applicant’s arguments, see pages 6 and 10-12 of the remarks filed on 6/18/2026, with respect to the double patenting and 35 USC 103 rejections have been fully considered and are persuasive. Therefore, the double patenting and 35 USC 103 rejections have been withdrawn.
Applicants’ arguments filed on 6/18/2026 regarding the 35 USC 101 rejections have been fully considered but they are not persuasive. Therefore, the 35 USC 101 rejections have been maintained.
Applicant first argues the 35 USC 101 rejection on pages 7-8 of the remarks in the substance that:
“Amended claim 1 does not fall within the Mathematical Calculation grouping or the Mental Processes grouping of Abstract Ideas. For example, claim 1 does not recite a mathematical calculation abstract idea because claim 1 does not recite any elements that are mathematical formulas. According to the USPTO's analysis for Examples 38 and 39, "While some of the limitations may be based on mathematical concepts, the mathematical concepts are not recited in the claims."4
In addition, claim 1 does not recite a mental process. In the analysis for claim 2 of Example 37, the USPTO stated that the claim elements quoted below are "action by a processor that cannot be practically applied in the mind… In addition, for Examples 38 and 39, the USPTO concluded that the claims are not mental processes because "the steps are not practically performed in the human mind."8
Like the claims in Examples 37-39, amended claim 1 cannot be practically performed in the human mind. Rather, the elements of claim 1 are an improvement to forming constant extensions in a very long instruction word (VLIW) processor using the circuits and operations recited in claim 1. The operations recited in claim 1 cannot be performed without a computer9 and do not represent the conventional use of generic computer elements. The novel operations are executed by an instruction decoder circuit
not by a human mind - and the instruction decoder circuit is configurable to provide the consequent extended values to a functional circuit.
The operations recited in amended claim 1 are not mathematical calculations and cannot be practically performed by a human. For at least these reasons, amended claim 1 does not fall within the Mathematical Calculation grouping or the Mental Processes grouping of Abstract Ideas.”
It appears the applicant is arguing above that claim 1 does not recite a mathematical concept nor a mental process. The applicant states that the claim does not recite a mathematical concept because the claim does not recite any mathematical formulas. The examiner respectfully disagrees because the examiner notes that the claim recites mathematical relationships similar to Digitech Image Techs., LLC v. Electronics for Imaging, Inc., 758 F.3d 1344, 1350, 111 USPQ2d 1717, 1721 (Fed. Cir. 2014) (see MPEP 2106.04(a)(2)(I(A) iv. organizing information and manipulating information through mathematical correlations). For example, the claim recites forming values by appending (e.g. concatenating) values to other values and thus discloses organizing and manipulating information using concatenation which is a mathematical operation which joins numbers in computer science. Furthermore, claims 2-3 explicitly recite the extending in claim 1 is sign-extension, which is a mathematical operation/relationship. Thus, the claims recite mathematical relationships, which are mathematical concepts.
Further, the applicant argues that the mental processes cannot be practically performed in the mind similarly to examples 37-39. However, the examiner respectfully disagrees. For example, looking to example 37 claim 2 it was deemed that it could not be practically performed in the mind because it required a processor to access computer memory indicative of application usage, based upon the claim limitation stating “determining the amount of use of each icon using a processor that tracks how much memory has been allocated to each application associated with each icon over a
predetermined period of time”. Said another way the “determining step” is not merely tied to a generic processor but a processor that tracks how much memory has been allocated. It is not the mere recitation of a “processor” that causes the steps to not practically be performed in the human mind, but the recitation of “a processor that tracks memory allocations”; merely adding “a processor” would be a generic computing component under MPEP 2106.05(f). The examiner notes that the instant application claims generic computing components by generically reciting a decoder and a functional circuit.
The examiner further notes the claims state forming values by appending values, then extending values, which can practically be performed in the human mind with the aid of pen and paper. The claims further merely recites generic computing components (e.g., decode circuit and functional circuit) used to decode and execute instructions. As all instruction processors include instruction decoders which decode instructions and instruction operands to provide values to an execution unit, the claimed components are generic computing components under MPEP 2106.05(f). The claims include no details of any circuitry or modification made to a decoder that would indicate or reflect some improvement to the functioning of a processor or claim a particular machine.
The applicant argues the elements reflect an improvement to a VLIW processor forming constant extensions. The examiner directs the applicant to MPEP 2106.05(a) which states “…the claim must be evaluated to ensure the claim itself reflects the disclosed improvement in technology…That is, the claim must include the components or steps of the invention that provide the improvement described in the specification.” The examiner notes the claim doesn’t indicate that the device includes a VLIW processor nor VLIW architecture packets that encode multiple operations/instructions. The claims merely recite generating values by combining values and extending values. Thus, no improvement to VLIW processors is reflected in the claim, because the claim merely recites a generic device with generic computing components (e.g. decoder and functional circuits).
19. Applicant then argues the 35 USC 101 rejection on pages 8-10 of the remarks in the substance that:
“Amended claim 1 recites a device comprising a functional circuit and an instruction decoder circuit configurable to form extended values. The Office should adopt the USPTO's analysis for Step 2A - Prong 2 and conclude that even "well-understood, routine, conventional subject matter can integrate an abstract idea into a practical application…. the Office found that the operations recited in claim 1 as previously presented amount to "generic computing components (e.g. functional unit, instruction decoder ...)."1 However, claim 1 as amended recites novel operations performed by an instruction decoder circuit to form extended values. Applicant respectfully submits that the Office should cite a prior art reference to prove that this specific ordered set of operations is an allegedly generic computing function.
The Office should not dismiss the improvement in extended values resulting from the operations recited in amended claim 1 because of the possible implementations for the improved constant extensions in VLIW processors. The Applicant's specification describes the practical applications for the extended values recited in claim 1
In addition, the operations recited in amended claim 1 provide the benefit to VLIW processors of forming an extended value using non-adjacent instructions in a single execute packet.16 Thus, amended claim 1 recites improved technical functioning for forming constant extensions, which is eligible subject matter under 35 U.S.C. § 101.”
The examiner notes that well-understood, routine and conventional considerations are not evaluated at step 2A prong 2, but at step 2B. Furthermore, it appears applicant is attempting to state that the decoder is not generic because it is performing novel operations. However, the limitations the applicant is referring to are the abstract ideas, thus applicant is merely implementing an abstract idea on a computer, as all computers have a decoder, implementing an abstract idea on a generic computer does not integrate the abstract idea into a practical application in Step 2A Prong Two nor add significantly more in Step 2B. (See MPEP 2106.05(f))
Furthermore, applicant argues the claim recites limitations that provide improvements to VLIW processors of forming extended values using non-adjacent instructions in a single packet. However, as stated in section 18 above, none of those improvements are reflected in the claim. MPEP 2106.05(a) states “…That is, the claim must include the components or steps of the invention that provide the improvement described in the specification.” Therefore, if extending values using non-adjacent instructions in a single packet provides an improvement to a VLIW processor that should be reflected in the claims.
20. The examiner suggests amending the claims to reflect an improvement to the functioning of a VLIW processor as argued above. For example, details on page 2 of specification and argued above discuss constant extension instructions being in a same execute packet as an instruction requiring constant extension, this appears to reflect greater flexibility in a VLIW processor (e.g. claiming the arrangement of the claimed instructions being non-adjacent instructions in a same instruction packet would reflect the argued improvement). (also, note claims 8-9 appear to state the instructions are adjacent which appears to conflict with the improvement the applicant argues above and applicant should consider this regarding future amendments)
Conclusion
21. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
22. Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY P SPANN whose telephone number is (571)431-0692. The examiner can normally be reached M-F, 9am-6pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COURTNEY P SPANN/Primary Examiner, Art Unit 2183
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