Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
DETAILED ACTION
In response to the Communications dated January 17, 2025, claims 1-13 are active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Foreign Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)
(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statements filed January 17, 2025 have been considered.
Claim Objections
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-10, 12 and 13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 5-9, 15 and 16 of U.S. Patent No. 12237014 [‘014]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘014
1. A semiconductor memory device, comprising: a bit line extending in a first direction; a first signal line extending in the first direction; a second signal line extending in the first direction, and arranged at one side of the first signal line in a second direction, the second direction crossing the first direction; a third signal line extending in the first direction, and arranged at one side of the second signal line in the second direction; a fourth signal line extending in the first direction, and arranged at one side of the third signal line in the second direction; a source line; a memory cell unit including a first selection transistor connected to the bit line, a second selection transistor connected to the source line, and a plurality of memory cells connected in series between the first selection transistor and the second selection transistor, the memory cells including first to fourth memory cells: a first word line connected to the first memory cell; a second word line connected to the second memory cell; a third word line connected to the third memory cell; a fourth word line connected to the fourth memory cell; a driver circuit configured to apply voltages to the first to the fourth signal lines; a first transistor including a first diffused layer connected to the first word line and a second diffused layer connected to the first signal line, the first diffused layer and the second diffused layer are arranged along the first direction; a second transistor including a third diffused layer connected to the second word line and a fourth diffused layer connected to the second signal line, arranged at one side of the first transistor in the second direction, the third diffused layer and the fourth diffused layer are arranged along the first direction; a third transistor including a fifth diffused layer connected to the third word line and a sixth diffused layer connected to the third signal line, arranged at one side of the second transistor in the second direction, the fifth diffused layer and the sixth diffused layer are arranged along the first direction; and a fourth transistor including a seventh diffused layer connected to the fourth word line and an eighth diffused layer connected to the fourth signal line, arranged at one side of the third transistor in the second direction, the seventh diffused layer and the eighth diffused layer are arranged along the first direction ,a common gate line extending in the second direction above the first transistor, the second transistor, the third transistor and the fourth transistor. wherein the first word line includes a first part extending in the second direction above the common gate line, the second word line includes a second part extending in the second direction above the common gate line, and the third word line includes a third part extending in the second direction above the common gate line.
1. A semiconductor memory device, comprising: a bit line extending in a first direction; a first signal line extending in the first direction; a second signal line extending in the first direction, and arranged at one side of the first signal line in a second direction, the second crossing the first direction; a third signal line extending in the first direction, and arranged at one side of the second signal line in the second direction; a fourth signal line extending in the first direction, and arranged at one side of the third signal line in the second direction; a source line; a memory cell unit including a first selection transistor connected to the bit line, a second selection transistor connected to the source line, and a plurality of memory cells connected in series between the first selection transistor and the second selection transistor, the memory cells including: a first memory cell, a second memory cell located between the first selection transistor and the first memory cell, a third memory cell located between the first selection transistor and the second memory cell, and a fourth memory cell located between the first selection transistor and the third memory cell; a first word line connected to the first memory cell; a second word line connected to the second memory cell; a third word line connected to the third memory cell; a fourth word line connected to the fourth memory cell; a driver circuit configured to apply voltages to the first to the fourth signal lines; a first transistor including a first diffused layer connected to the first word line and a second diffused layer connected to the first signal line, the first diffused layer and the second diffused layer are arranged along the first direction; a second transistor including a third diffused layer connected to the second word line and a fourth diffused layer connected to the second signal line, arranged at one side of the first transistor in the second direction, the third diffused layer and the fourth diffused layer are arranged along the first direction; a third transistor including a fifth diffused layer connected to the third word line and a sixth diffused layer connected to the third signal line, arranged at one side of the second transistor in the second direction, the fifth diffused layer and the sixth diffused layer are arranged along the first direction; and a fourth transistor including a seventh diffused layer connected to the fourth word line and an eighth diffused layer connected to the fourth signal line, arranged at one side of the third transistor in the second direction, the seventh diffused layer and the eighth diffused layer are arranged along the first direction, wherein the first word line includes a first part extending in the second direction above the second transistor, a second part extending in the second direction above the third transistor and a third part extending in the second direction above the fourth transistor, the second word line includes a fourth part extending in the second direction above the third transistor and a fifth part extending in the second direction above the fourth transistor, and the third word line includes a sixth part extending in the second direction above the fourth transistor, and wherein the second part of the first word line and the fourth part of the second word line are arranged in the first direction with a first interval, and the third part of the first word line, the fifth part of the second word line and the sixth part of the third word line are arranged in the first direction with the first intervals.
2. The device according to claim 1, wherein the first to third parts overlap with the common gate line when viewed in a third direction, the first to third directions crossing one another.
See claim 1 and remarks below.
3. The device according to claim 1, wherein the first to third parts overlap one another when viewed in the second direction.
See claim 1 and remarks below.
4. The device according to claim 1, wherein the second memory cell is located between the first selection transistor and the first memory cell, the third memory cell is located between the first selection transistor and the second memory cell, and the fourth memory cell is located between the first selection transistor and the third memory cell.
See claim 1 and remarks below regarding claims 1-3.
5. The device according to claim 4, wherein the memory cell unit is arranged at the other side of the first transistor in the second direction.
See claim 1 and remarks below regarding claims 1-3.
6. The device according to claim 4, wherein, when data is written into the first memory cell, the driver circuit applies: a first voltage to the first signal line, a second voltage to the second signal line, a third voltage to the third signal line, and a fourth voltage is applied to the fourth signal line, and wherein the first voltage is larger than the second voltage, the third voltage, and the fourth voltage, the second voltage is larger than the third voltage, and the fourth voltage is larger than the third voltage.
5. The device according to claim 4, wherein, when data is written into the first memory cell, the driver circuit applies: a first voltage to the first signal line, a second voltage to the second signal line, a third voltage to the third signal line, and a fourth voltage is applied to the fourth signal line, and wherein the first voltage is larger than the second voltage, the third voltage, and the fourth voltage, the second voltage is larger than the third voltage, and the fourth voltage is larger than the third voltage.
7. The device according to claim 6, wherein the second voltage is equal to the fourth voltage.
6. The device according to claim 5, wherein the second voltage is equal to the fourth voltage.
8. The device according to claim 6, wherein the third voltage turns off the second memory cell and the third memory cell regardless of held data.
7. The device according to claim 5, wherein the third voltage turns off the second memory cell and the third memory cell regardless of held data.
9. The device according to claim 6, wherein the third voltage is a positive voltage.
8. The device according to claim 5, wherein the third voltage is a positive voltage.
10. The device according to claim 1, wherein the semiconductor memory device is a NAND memory device.
9. The device according to claim 4, wherein the semiconductor memory device is a NAND memory device.
12. The device according to claim 1, wherein each of the second to the fourth word lines includes a crank portion.
15. The device according to claim 4, wherein each of the second to the fourth word lines includes a crank portion.
13. The device according to claim 12, wherein the second word line includes at least one of the crank portions, the third word line includes at least two of the crank portions, and the fourth word line includes at least three of the crank portions.
16. The device according to claim 15, wherein the second word line includes at least one of the crank portions, the third word line includes at least two of the crank portions, and the fourth word line includes at least three of the crank portions.
As can be seen from the above table, claim 1 of the present application broadly claims "a plurality of memory cells" connected in series, which encompasses any number of cells (including four or more). Claim 1 of the patent specifically limits or defines the structural arrangement and spatial location of four specific memory cells (first, second, third, and fourth). Adding specific structural designations (e.g., locating specific cells between the selection transistor and other cells) to a generic "plurality of memory cells" represents an obvious variation or simple optimization that does not yield an unexpected result. A generic claim does not become patentably distinct from a narrower species merely because the species adds structural details. Therefore, the patent renders the application unpatentable over ODP.
With respect to claim 2, introducing the limitation that the first to third parts overlap with the common gate line does not create a patentably distinct invention. It merely structurally defines how the parts physically interface within the Semiconductor Memory Device architecture. Arranging existing functional layers to overlap (such as a gate electrode overlapping a channel) is standard.
With respect to claim 3, reasons as set forth similar to claim 2.
With respect to claims 4 and 5, the core invention (a bit line, signal lines, a source line, and a memory unit with selection transistors) remains identical. The additional phrases do not provide an unexpected technical effect or solve a new problem; they simply detail one specific layout choice among a finite number of predictable alternatives.
For similar reasons, claims 6-10, 12 and 13 are rejected over claims 1, 5-9, 15 and 16 of patent ‘014.
Allowable Subject Matter
The following is an Examiner's statement of reasons for the indication of
allowable subject matter: the prior art of records does not show (in addition to the other
elements in the claim) the following:
With respect to claim 11. The device according to claim 1, wherein the first diffused layer, the second diffused layer and the common gate line form the first transistor, the third diffused layer, the fourth diffused layer and the common gate line form the second transistor, the fifth diffused layer, the sixth diffused layer and the common gate line form the third transistor, and the seventh diffused layer, the eighth diffused layer and the common gate line form the fourth transistor.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 June 25, 2026
Prosecution Insights