Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Status
This action is responsive to the amendment filed 16 September 2026. Claim 1 was amended; claims 2–12 are unchanged; claims 13–20 remain withdrawn. Claims 1–12 are examined.
The rejection of claims 1–12 under 35 U.S.C. § 112(b) set forth in the Office action mailed 1 July 2026 is withdrawn in view of the amendment to claim 1, which now recites a sensing unit before each later recitation of the sensing unit.
The rejections set forth in the Office action mailed 1 July 2026 — claims 1–4 under 35 U.S.C. § 102(a)(1) as anticipated by Li (US 2017/0193906 A1), or in the alternative under § 103 as obvious over Li, or in the alternative under § 103 as obvious over Li in view of Lee (US 2017/0154577 A1); and claims 5–12 under § 103 as obvious over Li in view of Yu (US 2015/0379909 A1), or in the alternative over Li as applied to claim 4 above and further in view of Yu, or in the alternative over Li in view of Lee as applied to claim 4 above and further in view of Yu — are withdrawn in view of the amendment to claim 1 and are replaced by the grounds below. The new grounds are necessitated by the amendment: a sensing driver external to the blocks, wherein the sensing driver comprises a sensing unit appears in no claim previously examined.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description:
S3, the third sensing line [e.g., Instant Specification Paragraph 122: the third block (BL3) may be connected to the third sensing unit 530 via the third sensing line (S3); Fig. 5: S1, S2, S34, S4 (as filed, sheet 4)] (Fig. 1 prints S1 to Sp and Fig. 5 prints S34; no figure prints S3).
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description:
S34 (Fig. 5) and Cst, Chd and VREF (Fig. 9).
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
(a) Paragraph 106 refers to the gate electrode of “the fifth transistor (T6)”; the fifth transistor is T5 throughout the paragraph and the specification (there is no sixth transistor) [e.g., Instant Specification Paragraph 106: A gate electrode of the fifth transistor (T6) is connected to the ith light-emitting control line (ELi), such that the fifth transistor (T5) may be turned on]. --(T5)-- is suggested.
(b) Paragraph 141 lists the pixels of the first sub-pixel column as “(SC11, SP21, SP31)”; SC1 is the column and the pixel is SP11 (see paragraph 160: SP11 to SP13) [e.g., Instant Specification Paragraph 141: the first sub-sensing line (S11) may be connected to the pixels (SC11, SP21, SP31) of the first sub-pixel column (SC1)]. --(SP11, SP21, SP31)-- is suggested.
(c) Paragraph 160 refers to “the third sub-pixel (SC13)”; the third sub-pixel is SP13 [e.g., Instant Specification Paragraph 160: The second switch circuit 512 may select the first sub-pixel (SP11) based the first selection signal (SEL1); Instant Specification Paragraph 160: select the third sub-pixel (SC13) based on the third selection signal (SEL3); Instant Specification Paragraph 159: The first to third sub-pixels (SP11 to SP13) may be included in the target line.]. --(SP13)-- is suggested. The same paragraph reads “based the first selection signal (SEL1)”; --based on the first selection signal (SEL1)-- is suggested.
(d) Paragraph 162, second sentence, is incomplete: “FIG. 9 is a diagram illustrating the structure in which a first sub-pixel and a first sensing unit.” The brief description of the drawings supplies the missing predicate [e.g., Instant Specification Paragraph 162: FIG. 9 is a diagram illustrating the structure in which a first sub-pixel and a first sensing unit.; Instant Specification Paragraph 39: FIG. 9 is a diagram illustrating the structure in which a first sub-pixel and a first sensing unit are connected.]. --… a first sub-pixel and a first sensing unit are connected.-- is suggested.
Appropriate correction is required.
Claim Interpretation
The following constructions apply throughout the grounds below, under the broadest reasonable interpretation consistent with the specification (MPEP 2111).
(a) Connected includes indirect connection: the specification states that a part described as connected to another part includes the case where the two are indirectly connected, that is, connected with another element interposed therebetween [e.g., Instant Specification Paragraph 50: with another element interposed therebetween].
(b) Block. The specification defines a block only by the sub-pixels it includes and by its connection to one sensing unit through one sensing line [e.g., Instant Specification Paragraph 121: Each of the first to fourth blocks (BL1 to BL4) may include a plurality of sub-pixels (SPs); Instant Specification Paragraph 122: The first block (BL1) may be connected to the first sensing unit 510 via the first sensing line (S1)]; no extent, shape or boundary is recited. A block therefore reads on any group of sub-pixels of the panel that is connected to one sensing unit through one sensing line — in Kim, the pixels PX_R, PX_G and PX_B whose readout lines RL1–RL3 join at the common readout line CRL1 (¶57, FIG. 3A), or the pixels served by one source driving chip 201–204 (¶70, FIG. 5).
(c) Sub-sensing line is a line of the sensing line connected to the sub-pixels of one color of the block. The claim does not require the sub-sensing lines to be electrically isolated from one another downstream of the sub-pixels, and it does not require the first and second initialization voltages to stand on the two sub-sensing lines at the same time; it recites two switches, two voltage nodes and two different voltages.
(d) Sensing node (claims 4–6) is the single node on the sensing-unit side of the selection switches to which the selection switches, the reset switch, the sensing capacitor and the input end of the analog front-end are connected, as the specification uses it [e.g., Instant Specification Paragraph 175: The first selection switch (SW_SEL1) may be connected between the first sub-sensing line (S11) and a sensing node (SD)]. In the combination applied to claims 4–12 that node is the node between Kim’s sampling transistor ST1 and the ADC 223, at which Kim connects the sampling capacitor Cp (¶93, FIG. 6B); every element of claims 5 and 6 is applied at that node.
(e) Initialization voltage node is any node at which the recited initialization voltage is applied; no separate generator per node is recited. Reset switch … turned on in response to a reset signal recites a switch between the sensing node and ground and a control signal that turns it on; no further function is recited.
Claim Rejections - 35 USC § 102 / 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1 is rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Kim (US 2023/0109314 A1);
or, in the alternative, under 35 U.S.C. § 103 as being unpatentable over Kim;
or, in the alternative, under 35 U.S.C. § 103 as being unpatentable over Kim in view of Lee (US 2017/0154577 A1).
Regarding claim 1, Kim discloses a display device comprising: [e.g., Kim, Fig. 1: DD, DP, PX; Paragraph 45: Each of the plurality of pixels PX may include a light emitting element ED (see FIG. 6A) and a pixel driving circuit (or a pixel circuit) PXC (see FIG. 6A) for controlling light emission of the light emitting element ED.]
a display panel comprising a plurality of blocks, [e.g., Kim, Paragraph 57: the first to third readout lines RL1 to RL3 may be electrically connected to a common readout line CRL1.; Paragraph 59: two adjacent readout lines among the plurality of readout lines RL1 to RLm may be electrically connected to each other, or four adjacent readout lines among the plurality of readout lines RL1 to RLm may be electrically connected to each other.; Paragraph 70: the display device DD may include a plurality of source driving chips 201, 202, 203, and 204 in which the source drivers 200 are respectively embedded.; Fig. 3A: PX_R, PX_G, PX_B, CRL1; Fig. 5: 201–204, DA]
wherein each of the blocks comprises a plurality of sub-pixels; and [e.g., Kim, Paragraph 57: the plurality of pixels PX may include a plurality of red pixels, a plurality of green pixels, and a plurality of blue pixels.; Fig. 3A: PX_R, PX_G, PX_B]
a sensing driver external to the blocks, [e.g., Kim, Fig. 2: 200, 220 (Sensing Driver); Paragraph 49: the source driver 200 may be formed in the form of or defined by at least one chip.; Paragraph 49: the data driver 210 and the sensing circuit 220 may be embedded in the chip.; Paragraph 70: the display device DD may include a plurality of source driving chips 201, 202, 203, and 204 in which the source drivers 200 are respectively embedded.; Fig. 5: 201, 202, 203, 204, FCB1–FCB4, PCB, DA, NDA]
wherein the sensing driver comprises a sensing unit connected to a first block among the blocks via a sensing line, [e.g., Kim, Paragraph 88: The sensing circuit 220 (see FIG. 2) may be connected to the plurality of readout lines RL1 to RLm.; Paragraph 140: an embodiment of a sensing circuit 220a may include a first initialization circuit unit 221a, a second initialization circuit unit 221b, a sampling circuit unit 222, and an ADC 223; Fig. 4: 220, 221, 222, 223; Fig. 9: 220a, 221a, 221b, 222, 223; Fig. 3A: CRL1]
wherein the sensing line comprises a first sub-sensing line connected to sub-pixels which emit light in a first color among sub-pixels included in the first block [e.g., Kim, Paragraph 57: A first red pixel PX_R of the plurality of red pixels is connected to the first data line DL1 and the first readout line RL1.; Fig. 1: RL1; Fig. 3A: RL1, PX_R] and
a second sub-sensing line connected to sub-pixels which emit light in a second color different from the first color among the sub-pixels included in the first block, [e.g., Kim, Paragraph 57: A first green pixel PX_G of the plurality of green pixels is connected to a second data line DL2 and a second readout line RL2.; Fig. 3A: RL2, PX_G]
the sensing unit comprises: a sensing capacitor; [e.g., Kim, Paragraph 93: The sampling circuit units 222 or 222a may further include various circuit elements (e.g., the sampling capacitor Cp) for sampling the sensing signals; Paragraph 90: a sampling circuit unit 222a may further include a sampling capacitor Cp connected to the first readout line RL1 through a sampling transistor ST1. The sampling capacitor Cp may store a signal sampled through the sampling transistor ST1.; Paragraph 147: The sampling circuit unit 222 illustrated in FIG. 9 may include a plurality of sampling transistors respectively connected to the plurality of readout lines RL1 to RLm; Fig. 6B: Cp, 222a; Fig. 9: 222]
a first initialization switch connected between a first initialization voltage node, to which a first initialization voltage is applied, and the first sub-sensing line; and [e.g., Kim, Paragraph 148: The first initialization transistor ITa may include a first electrode that receives a first initialization voltage VINIT1, a second electrode connected to the first readout line RL1, and a third electrode that receives the first initialization control signal ICS1; Paragraph 145: a plurality of first initialization transistors ITa respectively connected to the plurality of readout lines RL1 to RLm; Fig. 10: ITa, VINIT1, ICS1, RL1, N2, 221a]
a second initialization switch connected between a second initialization voltage node, to which a second initialization voltage is applied, and the second sub-sensing line, and [e.g., Kim, Paragraph 149: The second initialization transistor ITb may include a first electrode that receives a second initialization voltage VINIT2, a second electrode connected to the first readout line RL1, and a third electrode that receives the second initialization control signal ICS2; Paragraph 145: a plurality of second initialization transistors ITb respectively connected to the plurality of readout lines RL1 to RLm; Paragraph 146: the initialization circuit units 221a and 221b may further include first and second initialization transistors respectively connected to the remaining readout lines RL2 to RLm; Fig. 10: ITb, VINIT2, ICS2, 221b; Fig. 9: 221a, 221b, RL1–RLm]
the first initialization voltage and the second initialization voltage are different from each other. [e.g., Kim, Paragraph 149: the second initialization voltage VINIT2 may have a lower voltage level than the first initialization voltage VINIT1; Paragraph 170: after performing a first initialization process of preemptively lowering the potential VN1 of the first node N1 to the second initialization voltage VINIT2 through the second initialization circuit unit 221b, a second initialization process of lowering the potential VN1 of the first node N1 to the first initialization voltage VINIT1 may be performed; Fig. 12A: ICS1, ICS2, IAP1, VINIT1] (e.g., see Paragraphs 44–189)
Kim’s sensing circuit 220a (FIG. 9) comprises the first and second initialization circuit units 221a and 221b, whose first and second initialization transistors ITa and ITb are connected to each of the readout lines RL1 to RLm (¶145–¶146), and the sampling circuit unit 222 (¶140, ¶147);
Kim states that the sampling circuit unit 222 may include the sampling capacitor Cp [e.g., Kim, Paragraph 93: The sampling circuit units 222 or 222a may further include various circuit elements (e.g., the sampling capacitor Cp)].
The readout lines RL1 and RL2 are distinct lines, each connected to the pixels of one color (¶57); their downstream connection at the common readout line CRL1, which Kim describes as one embodiment among others (¶57, ¶59), leaves each line connected to its own initialization transistors, and claim 1 does not recite that the two initialization voltages are applied to the two lines at the same time (interpretation (c) above).
Kim applies the second initialization voltage VINIT2 and then the first initialization voltage VINIT1 in two successive stages (¶170; FIG. 12A).
Should it be shown that Kim discloses the sensing unit comprises: a sensing capacitor together with the first and second initialization switches, as instantly claimed, with insufficient specificity — on the ground that the sampling capacitor Cp is drawn only in the sensing circuit 220-1 of FIG. 6B and the two initialization transistors only in the sensing circuit 220a of FIGS. 9–10:
Kim expressly states that the sampling circuit unit 222 of the sensing circuit 220a may include the sampling capacitor Cp (¶93), and that the capacitor stores the signal sampled through the sampling transistor ST1 (¶90).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the sampling capacitor Cp in the sampling circuit unit 222 of Kim’s sensing circuit 220a, as Kim itself proposes, in order to store the sampled sensing signal for conversion by the ADC 223 (¶90, ¶65). KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007); Graham v. John Deere Co., 383 U.S. 1 (1966).
Should it be shown that Kim discloses a second initialization switch connected between a second initialization voltage node, to which a second initialization voltage is applied, and the second sub-sensing line, and the first initialization voltage and the second initialization voltage are different from each other, as instantly claimed, with insufficient specificity:
Lee discloses first and second initialization (charging) voltages that are different from each other according to the color of the sub-pixel [e.g., Lee, Paragraph 80: a red organic light emitting diode (R), a green organic light emitting diode (G), and a blue organic light emitting diode (B) are supplied with different charging voltages based on a color emitted therefrom; Paragraph 83: The levels of charging voltages may be in a relationship of the first charging voltage aV>the second charging voltage bV<the third charging voltage cV; Fig. 11: 160, aV, bV, cV (three levels)],
applied through the switches of the data driver’s channel to the sensing line of the selected color sub-pixel, the red, green and blue sub-pixels’ lines entering the multiplexer of the driver separately [e.g., Lee, Paragraph 65: the data driver 130 may drive a voltage output switches SCS and PRE, which are provided inside the data driver 130, to output a data voltage of a charging voltage (or a pre-charge voltage) through its N-th input/output channel; Paragraph 57: the first transistor Ms electrically connects a N-th th input/output channel of the data driver 130 to the N-th sensing line SL; Paragraph 63: The mux unit MUX selectively senses one of a red subpixel SPr, a green subpixel SPg, and a blue subpixel SPb; Fig. 4: VPREO, SCS, PRE, Ms, SL, T2, Charging Path; Fig. 6: 130, MUX 3:1, SPr, SPg, SPb (three lines into the MUX)].
Kim and Lee are analogous art because they are from the shared inventive field of light emitting diode display devices whose sensing circuits initialize a sensing line and sense a pixel through it.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to apply Lee’s different, color-dependent initialization voltages through Kim’s first and second initialization transistors to Kim’s first and second readout lines, so that the sub-pixels of each color are initialized to a level suited to that color, whereby sensing accuracy improves and a short sensing time is beneficial [e.g., Lee, Paragraph 90: as the independent voltages aV, bV, and cV are applied to the red organic light emitting diode (R), the green organic light emitting diode (G), and the blue organic light emitting diode (B), sensing accuracy improves and a short sensing time is beneficial; Paragraph 8: an organic light emitting diode shows different emission efficiency and deterioration speed (time) depending on the color emitted therefrom].
Moreover, it would have been obvious to one of ordinary skill in the art before the effective filing date because all the claimed elements were known in the prior art and one skilled in the art could have combined Lee’s color-dependent initialization voltages with Kim’s initialization transistors as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art. KSR, 550 U.S. 398; Graham, 383 U.S. 1.
Claim Rejections - 35 USC § 103
Claims 2–4 are rejected under 35 U.S.C. § 103 as being unpatentable over Kim as applied to claim 1 above, and further in view of Lee; or, in the alternative, under 35 U.S.C. § 103 as being unpatentable over Kim in view of Lee as applied to claim 1 above.
Regarding claim 2, Kim discloses the sensing line further comprises a third sub-sensing line connected to sub-pixels which emit light in a third color different from the first color and the second color among the sub-pixels included in the first block, [e.g., Kim, Paragraph 57: A first blue pixel PX_B of the plurality of blue pixels is connected to a third data line DL3 and a third readout line RL3.; Fig. 3A: RL3, PX_B]
the sensing unit further comprises a third initialization switch connected between a third initialization voltage node, to which a third initialization voltage is applied, and the third sub-sensing line, and [e.g., Kim, Paragraph 145: a plurality of first initialization transistors ITa respectively connected to the plurality of readout lines RL1 to RLm; Paragraph 146: the initialization circuit units 221a and 221b may further include first and second initialization transistors respectively connected to the remaining readout lines RL2 to RLm; Fig. 9: 221a, 221b, RL1–RLm]
Kim does not expressly disclose: the first initialization voltage, the second initialization voltage, and the third initialization voltage are different from each other.
Kim discloses two initialization voltages, applied to every readout line by its first and second initialization transistors [e.g., Kim, Paragraph 149: the second initialization voltage VINIT2 may have a lower voltage level than the first initialization voltage VINIT1]; the third initialization transistor on the third readout line RL3 receives one of those two voltages, so Kim does not expressly disclose a third initialization voltage different from both.
Lee discloses: the first initialization voltage, the second initialization voltage, and the third initialization voltage are different from each other. [e.g., Lee, Paragraph 84: the above example is a case where each organic light emitting diode has different characteristics; Paragraph 90: organic light emitting diodes are sensed using independent charging voltages aV, bV, and cV based on colors emitted therefrom; Paragraph 80: first to third charging voltages aV to cV are applied for a predetermined time t0 so as to sense organic light emitting diodes independently; Fig. 11: aV, bV, cV drawn at three different levels]
Lee’s first, second and third charging voltages aV, bV and cV are drawn at three different levels (FIG. 11) and are the case Lee describes for organic light emitting diodes whose characteristics differ from one another [e.g., Lee, Paragraph 84: the above example is a case where each organic light emitting diode has different characteristics; Paragraph 90: organic light emitting diodes are sensed using independent charging voltages aV, bV, and cV based on colors emitted therefrom; Paragraph 80: first to third charging voltages aV to cV are applied for a predetermined time t0 so as to sense organic light emitting diodes independently; Fig. 11: aV, bV, cV drawn at three different levels],
which Lee states is the general case for diodes of different colors [e.g., Lee, Paragraph 8: an organic light emitting diode shows different emission efficiency and deterioration speed (time) depending on the color emitted therefrom].
Lee separately describes the case in which two of the three diodes have the same characteristics and two of the voltages are equal [e.g., Lee, Paragraph 84: if two organic light emitting diodes have the same characteristics and only one organic light emitting diode has different characteristics, the levels of charging voltages may be in a relationship of the first charging voltage (aV)=the second charging voltage (bV)<the third charging voltage (cV)]; that alternative is expressly the exception for two diodes with the same characteristics, and it does not withdraw the three-different-voltage case that Lee illustrates and applies to the red, green and blue diodes.
Kim and Lee are analogous art for the reason given at claim 1.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to supply Kim’s first, second and third readout lines through their respective initialization transistors with Lee’s three different, color-dependent voltages, so that each color is sensed independently with improved sensing accuracy and a shorter sensing time [e.g., Lee, Paragraph 90: as the independent voltages aV, bV, and cV are applied to the red organic light emitting diode (R), the green organic light emitting diode (G), and the blue organic light emitting diode (B), sensing accuracy improves and a short sensing time is beneficial; Paragraph 8: an organic light emitting diode shows different emission efficiency and deterioration speed (time) depending on the color emitted therefrom]. KSR, 550 U.S. 398; Graham, 383 U.S. 1.
Regarding claim 3, Kim further discloses the first to third initialization switches are turned on in response to a voltage application signal applied thereto during an active interval of a frame. [e.g., Kim, Paragraph 148: The first initialization transistor ITa may initialize the potential of the first readout line RL1 to the first initialization voltage VINIT1 in response to the first initialization control signal ICS1; Paragraph 149: The second initialization transistor ITb may initialize the potential of the first readout line RL1 to the second initialization voltage VINIT2 in response to the second initialization control signal ICS2; Paragraph 101: during the display periods DT1 and DT2, the first readout line RL1 may have a state of being initialized to the initialization voltage VINIT; Paragraph 96: The display periods DT1 and DT2 may be periods in which an image is substantially displayed; Fig. 10: ICS1, ICS2; Fig. 7: DT1, DT2; Fig. 12A: ICS1 (IP, at both ends of BT1)]
Kim’s initialization transistors are turned on in response to the initialization control signals ICS1 and ICS2 (¶148–¶149), and Kim states that the readout line is in the initialized state during the display periods DT1 and DT2 (¶101), which are the periods in which the image is displayed (¶96); FIG. 12A draws ICS1 high at both boundaries of the blank period BT1, that is, in the display periods on either side of it.
Regarding claim 4, Kim further discloses the sensing unit further comprises: a first selection switch connected between the first sub-sensing line and a sensing node, wherein the first selection switch is turned on in response to a first selection signal; [e.g., Kim, Paragraph 93: The sampling transistor ST1 includes a first electrode connected to the second node N2, a second electrode connected to the ADC 223 (see FIG. 4), and a third electrode that receives the sampling control signal SCS; Paragraph 147: The sampling circuit unit 222 illustrated in FIG. 9 may include a plurality of sampling transistors respectively connected to the plurality of readout lines RL1 to RLm; Fig. 10: ST1, SCS, N2, 222; Fig. 9: 222, SM1–SMm]
a second selection switch connected between the second sub-sensing line and the sensing node, wherein the second selection switch is turned on in response to a second selection signal; and [e.g., Kim, Paragraph 147: the sampling circuit unit 222 may further include sampling transistors respectively connected to the remaining readout lines RL2 to RLm]
a third selection switch connected between the third sub-sensing line and the sensing node, wherein the third selection switch is turned on in response to a third selection signal, and [e.g., Kim, Paragraph 147: a plurality of sampling transistors respectively connected to the plurality of readout lines RL1 to RLm; Fig. 9: 222, RL1–RLm, SM1–SMm]
the first to third selection signals are applied during a blank interval after the active interval. [e.g., Kim, Paragraph 96: the blank periods BT1 and BT2 may be used as sensing periods for sensing the characteristic of each of the pixels PX through the sensing circuit 220; Paragraph 118: During the sampling period SMP, the sampling circuit unit 222 may receive the sensing signal through the first readout line RL1; Fig. 7: BT1, BT2, ROP1; Fig. 8A: SMP, SCS]
Should it be shown that Kim discloses first, second and third selection switches turned on in response to first, second and third selection signals, as instantly claimed, with insufficient specificity:
Lee discloses first, second and third selection switches, one per sub-pixel color, connected between the color sub-pixels’ sensing lines and a common sensing node, each turned on in response to its own selection signal [e.g., Lee, Paragraph 63: The mux unit MUX selectively senses one of a red subpixel SPr, a green subpixel SPg, and a blue subpixel SPb; Paragraph 89: a red organic light emitting diode included in a red subpixel is sensed if SMux3 drops from logic high to logic low; Fig. 6: MUX 3:1, SPr, SPg, SPb, SH; Fig. 8: SMux1, SMux2, SMux3].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to select Kim’s readout lines into the sampling circuit one color at a time with Lee’s multiplexer and per-color selection signals, so that a target sub-pixel of a chosen color can be selected for sensing and the sensing time shortened [e.g., Lee, Paragraph 88: it is possible to select a target to sense in the first embodiment of the present disclosure, and thus, a short sensing time is beneficial]; Kim already performs the sensing in the blank periods [e.g., Kim, Paragraph 96: the blank periods BT1 and BT2 may be used as sensing periods]. KSR, 550 U.S. 398; Graham, 383 U.S. 1.
Claims 5 and 6 are rejected under 35 U.S.C. § 103 as being unpatentable over Kim in view of Lee as applied to claim 4 above, and further in view of Yu (US 2015/0379909 A1).
Regarding claim 5, Kim further discloses the sensing capacitor connected between the sensing node and the ground power supply. [e.g., Kim, Paragraph 93: The sampling circuit units 222 or 222a may further include various circuit elements (e.g., the sampling capacitor Cp) for sampling the sensing signals; Fig. 6B: Cp (to ground), ST1, 222a]
Kim and Lee do not expressly disclose the sensing unit further comprises: a reset switch connected between the sensing node and a ground power supply, wherein the reset switch is turned on in response to a reset signal; and
Kim connects the sampling capacitor Cp between the node on the ADC side of the sampling transistor ST1 — the sensing node (interpretation (d)) — and ground (FIG. 6B; ¶93), and Lee’s sensing circuit is described as a multiplexer, sample holder, scaler, amplifier and analog-digital converter [e.g., Lee, Paragraph 61: a sensing circuit of the driving driver 130 includes a mux unit MUX, a sample holder SH, a scaler SCAL, an amplifier AMP, a buffer, BUF, switch units SWa to SWc, and an analog-digital converter ADC]; neither expressly discloses a switch connected between that node and a ground power supply and turned on in response to a control signal.
Yu discloses the sensing unit further comprises: a reset switch connected between the sensing node and a ground power supply, wherein the reset switch is turned on in response to a reset signal; and [e.g., Yu, Paragraph 86: a second noise cancelling switch HOLD_EG connected between the first output node NO_O and the ground power source GND; Paragraph 110: the second noise cancelling switches HOLD_EG are turned on to connect the nodes NO_O of the sampling & differential capacitors CS to the ground power source; Paragraph 78: the timing controller 11 may generate a control signal CON for each driving mode and control the switching timing of internal switches; Fig. 7: HOLD_EG, NO_O, GND, CS]
Yu’s switch HOLD_EG connects the node NO_O, at which one plate of the sampling capacitor CS is connected, to the ground power source, and is turned on under the control signal of the timing controller [e.g., Yu, Paragraph 86: a second noise cancelling switch HOLD_EG connected between the first output node NO_O and the ground power source GND; Paragraph 110: the second noise cancelling switches HOLD_EG are turned on to connect the nodes NO_O of the sampling & differential capacitors CS to the ground power source; Paragraph 78: the timing controller 11 may generate a control signal CON for each driving mode and control the switching timing of internal switches; Fig. 7: HOLD_EG, NO_O, GND, CS];
the other plate of CS is likewise connected to ground through the switch HOLD_OG [e.g., Yu, Paragraph 86: a sampling & differential capacitor CS connected between a first output node NO_O of the first current integrator CI1 and a second output node NO_E of the second current integrator CI2; Paragraph 87: The first noise cancelling switch HOLD_OG connects the second output node NO_E with the ground power source GND; Fig. 7: CS, NO_O, NO_E, HOLD_OG, HOLD_EG, GND].
Yu’s purpose is to remove common noise components from the sampled value and so provide shorter sensing time and higher sensing performance [e.g., Yu, Paragraph 85: The sample & hold unit S&H increases sensing accuracy by removing common noise components (including leakage current components) from the first and second sampled values Vb and Va by noise cancellation; Paragraph 16: An aspect of this document is to provide an organic light emitting display which offers shorter sensing time and higher sensing performance when sensing electrical characteristics of a driving element].
Kim, Lee and Yu are analogous art because they are from the shared inventive field of light emitting diode display devices with sensing circuits in the data driver that sense the pixels through sensing lines.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide, at the sensing node of the combination of Kim and Lee — the node at which Kim’s sampling capacitor Cp is connected to ground — a switch connected between that node and the ground power supply and turned on by a control signal, as Yu provides at the node of its sampling capacitor, in order to discharge the sampling capacitor and remove common noise components from the sampled value before conversion [e.g., Yu, Paragraph 85: The sample & hold unit S&H increases sensing accuracy by removing common noise components (including leakage current components) from the first and second sampled values Vb and Va by noise cancellation; Paragraph 16: An aspect of this document is to provide an organic light emitting display which offers shorter sensing time and higher sensing performance when sensing electrical characteristics of a driving element]. KSR, 550 U.S. 398; Graham, 383 U.S. 1.
Regarding claim 6, Yu further discloses the sensing unit further comprises: an analog front-end, to which the sensing node and a driving voltage node are connected at an input end thereof; and [e.g., Yu, Paragraph 83: The first current integrator CI1 comprises a first amplifier AMP_O comprising an inverting input terminal (−) connected to an odd-numbered one of the sensing lines 14B via an odd sensing channel CH_O; Paragraph 83: a non-inverting input terminal (+) receiving a reference voltage VREF; Fig. 7: AMP_O, CH_O, Nx, VREF, Vb]
an analog-to-digital converter which converts a voltage output from the analog front-end into a data value. [e.g., Yu, Paragraph 88: The ADC converts the output Vout, from which the common noise components are removed, into a digital sensed value; Paragraph 82: a sample & hold unit S&H that obtains an analog integrated value, which equals the difference between the sampled values input from the first and second current integrators CI1 and CI2 and from which common noise components are removed, and supplies it as an output Vout to the ADC; Fig. 7: ADC, Vout] [e.g., Kim, Paragraph 65: The ADC 223 converts the sampled signals SM1 to SMm outputted from the sampling circuit unit 222 into sensing data SD1 to SDm in a digital form; Paragraph 66: the sensing circuit 220 may further include a scaler disposed between the sampling circuit unit 222 and the ADC 223; Fig. 4: 222, 223]
Yu’s amplifier AMP_O receives the sensed line at its inverting input and the reference voltage VREF at its non-inverting input, and its output, after sampling, is supplied to the ADC (¶82–¶83). In the combination the amplifier is placed between Kim’s sampling circuit unit 222 and the ADC 223, where Kim places its optional scaler (¶66), so that the sensing node of interpretation (d) is connected at the amplifier’s input end.
The reason to combine given at claim 5 applies.
Claims 7–9, 11 and 12 are rejected under 35 U.S.C. § 103 as being unpatentable over Kim in view of Lee and Yu as applied to claim 6 above, and further in view of Le Roy (US 2009/0184900 A1).
Regarding claim 7, Yu further discloses when the first selection switch is turned on, a first driving voltage is applied to the driving voltage node, [e.g., Yu, Paragraph 55: the input terminals (+,−) and output terminal of the amplifier AMP, the sensing line 14B, and the second node N2 are all initialized to the reference voltage VREF; Paragraph 98: The output level of the sensing units UNIT#1 to UNIT#m applied to the ADC differs according to the reference voltage VREF or equalization voltage AVREF]
Kim, Lee and Yu do not expressly disclose when the second selection switch is turned on, a second driving voltage is applied to the driving voltage node, when the third selection switch is turned on, a third driving voltage is applied to the driving voltage node, and the first to third driving voltages are different from each other.
Yu applies the reference voltage VREF to the driving voltage node of the amplifier while a channel is sensed and states that the level applied determines the output applied to the ADC [e.g., Yu, Paragraph 55: the input terminals (+,−) and output terminal of the amplifier AMP, the sensing line 14B, and the second node N2 are all initialized to the reference voltage VREF; Paragraph 98: The output level of the sensing units UNIT#1 to UNIT#m applied to the ADC differs according to the reference voltage VREF or equalization voltage AVREF];
Lee discloses that supplying color-dependent charging voltages reduces the sensing range for the red, green and blue organic light emitting diodes and so improves sensing accuracy [e.g., Lee, Paragraph 87: the independent charging voltages aV, bV, and cV are respectively supplied to the red red organic light emitting diode (R), the green organic light emitting diode (G), and the blue organic light emitting diode (B), as shown in FIG. 11. Therefore, if sensing is performed after the predetermined time t1, a sensing range Δ2V with respect to the red OLED (R), the green OLED (G), and the blue OLED (B) may be reduced. Since the sensing range is reduced, the sensing accuracy may improve; Fig. 11: Sensing Reference Voltage, Δ2V].
None of the three expressly discloses that the voltage applied to the driving voltage node when the second and the third selection switch are respectively turned on differs from that applied when the first is turned on.
Le Roy discloses: when the second selection switch is turned on, a second driving voltage is applied to the driving voltage node, [e.g., Le Roy, Paragraph 99: The output of the generator 38 is connected to the inverting input - of the amplifier 35; Paragraph 98: The generator 38 is a generator adapted for delivering a reference voltage which is fixed during settings of the display device and which is specific to each column. As a variant, it is also possible to use a variable voltage generator; the variation of the reference voltage is a function of the column of emitters 21A which is addressed; Fig. 2: 20A, 35, 38, 44, 54]
when the third selection switch is turned on, a third driving voltage is applied to the driving voltage node, and the first to third driving voltages are different from each other. [e.g., Le Roy, Paragraph 106: there will be three different values of reference voltage, a first value Vref.R common to the set of red emitters of a first column, a second value Vref.G common to the set of green emitters with a second column and a third value Vref.B common to the set of blue emitters of a third column; Paragraph 105: The reference voltage values of the directories 54 of each column are fixed here as a function of the colour of the emitters of a column 21A; Paragraph 82: The emitters of three adjacent columns are associated in succession with the colours red, green and blue]
Le Roy’s drive unit applies a reference voltage to an input of its amplifier 35 from a generator 38, and Le Roy states that, as a variant, the generator is a variable voltage generator whose reference voltage varies as a function of the column of emitters being addressed [e.g., Le Roy, Paragraph 99: The output of the generator 38 is connected to the inverting input - of the amplifier 35; Paragraph 98: The generator 38 is a generator adapted for delivering a reference voltage which is fixed during settings of the display device and which is specific to each column. As a variant, it is also possible to use a variable voltage generator; the variation of the reference voltage is a function of the column of emitters 21A which is addressed; Fig. 2: 20A, 35, 38, 44, 54];
the reference voltage values are three, one for the red, one for the green and one for the blue emitters, different from each other [e.g., Le Roy, Paragraph 106: there will be three different values of reference voltage, a first value Vref.R common to the set of red emitters of a first column, a second value Vref.G common to the set of green emitters with a second column and a third value Vref.B common to the set of blue emitters of a third column; Paragraph 105: The reference voltage values of the directories 54 of each column are fixed here as a function of the colour of the emitters of a column 21A; Paragraph 82: The emitters of three adjacent columns are associated in succession with the colours red, green and blue],
because emitters of different colors exhibit different current-voltage characteristics [e.g., Le Roy, Paragraph 104: The emitters associated with different colours exhibit different current-voltage characteristics, as may be seen in FIG. 12. Consequently, it is necessary to apply different voltages to the terminals of a red emitter and to the terminals of a blue emitter to obtain the same luminance and the same value of the current passing through these emitters; Paragraph 105: These reference values are established so as to compensate for the variations between the current-voltage electrical characteristics and/or luminous characteristics of the various emitters of the device].
Kim, Lee, Yu and Le Roy are analogous art because they are from the shared inventive field of light emitting diode display devices that compensate the differing characteristics of light-emitting sub-pixels of different colors, and Le Roy is also reasonably pertinent to the problem the inventor addresses, a sensing range that depends on the color of the sub-pixel being sensed, which Lee identifies (¶87).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to apply, in the combination of Kim, Lee and Yu, a first, a second and a third reference voltage to the driving voltage node of the analog front-end when the first, the second and the third selection switch respectively is turned on, the three being different from each other as Le Roy’s variable generator varies its reference voltage with the color of the emitters addressed, so that the reference level of the front-end matches the current-voltage characteristic of the color being sensed and the sensing range for each color is reduced [e.g., Le Roy, Paragraph 104: The emitters associated with different colours exhibit different current-voltage characteristics, as may be seen in FIG. 12. Consequently, it is necessary to apply different voltages to the terminals of a red emitter and to the terminals of a blue emitter to obtain the same luminance and the same value of the current passing through these emitters; Paragraph 105: These reference values are established so as to compensate for the variations between the current-voltage electrical characteristics and/or luminous characteristics of the various emitters of the device] [e.g., Lee, Paragraph 87: the independent charging voltages aV, bV, and cV are respectively supplied to the red red organic light emitting diode (R), the green organic light emitting diode (G), and the blue organic light emitting diode (B), as shown in FIG. 11. Therefore, if sensing is performed after the predetermined time t1, a sensing range Δ2V with respect to the red OLED (R), the green OLED (G), and the blue OLED (B) may be reduced. Since the sensing range is reduced, the sensing accuracy may improve; Fig. 11: Sensing Reference Voltage, Δ2V]. KSR, 550 U.S. 398; Graham, 383 U.S. 1.
In the alternative, and independently of Le Roy:
Lee itself identifies the finite set of options for the levels of three color-dependent voltages — all three different, for diodes whose characteristics all differ, or two equal and one different, for two diodes with the same characteristics [e.g., Lee, Paragraph 84: the above example is a case where each organic light emitting diode has different characteristics; Paragraph 90: organic light emitting diodes are sensed using independent charging voltages aV, bV, and cV based on colors emitted therefrom; Paragraph 80: first to third charging voltages aV to cV are applied for a predetermined time t0 so as to sense organic light emitting diodes independently; Fig. 11: aV, bV, cV drawn at three different levels] [e.g., Lee, Paragraph 84: if two organic light emitting diodes have the same characteristics and only one organic light emitting diode has different characteristics, the levels of charging voltages may be in a relationship of the first charging voltage (aV)=the second charging voltage (bV)<the third charging voltage (cV)] — and gives the reason to choose different levels for different colors, a reduced sensing range for each color (¶87).
Choosing, from that identified and finite set of predictable options, three different reference voltages for the three colors at the front-end’s driving voltage node would have been obvious to try to one of ordinary skill in the art before the effective filing date, with a reasonable expectation of success (MPEP 2143(I)(E)). KSR, 550 U.S. 398; Graham, 383 U.S. 1.
Regarding claim 8, Kim discloses a blank interval comprising a reference scan period, a sampling period and a rewriting period, and Yu discloses the pattern data (Le Roy is applied as at claim 7):
the blank interval comprises a first interval, a second interval, and a third interval, [e.g., Kim, Paragraph 106: a driving scan signal activated in each of the blank periods BT1 and BT2 among the driving scan signals SC1 to SCn may include a reference scan period and a rewriting period; Paragraph 105: the first driving scan signal SC1 among the plurality of driving scan signals SC1 to SCn may be activated during the first blank period BT1; Paragraph 113: a reference data signal Vref is provided to the first data line DL1 during the first reference scan period RSP1 of the first blank period BT1; Fig. 7: BT1, RSP1, RWP1; Fig. 8A: BT1, RSP1, SMP, RWP1, SC1, SCS]
during the first interval, a data signal corresponding to pattern data is applied to sub-pixels included in a target sub-pixel row including a target sub-pixel, [e.g., Yu, Paragraph 74: The sensing data voltage comprises a data voltage for a given grayscale that generates a pixel current (the source-drain current Ids of the driving TFT) greater than 0 and a data voltage for a black gray scale that suppresses the generation of the pixel current; Paragraph 107: In the odd sensing period, the data voltage for a given grayscale is applied simultaneously to the pixels connected to the odd sensing lines through the data lines, and the data voltage for a black grayscale is applied simultaneously to the pixels connected to the even sensing lines through the data lines]
during the second interval after the first interval, the target sub-pixel generates a driving current based on the pattern data, and the sensing unit generates sensing data based on the driving current, [e.g., Kim, Paragraph 118: After the first reference scan period RSP1 ends, the sampling control signal SCS may be activated; Paragraph 118: During the sampling period SMP, the sampling circuit unit 222 may receive the sensing signal through the first readout line RL1; Paragraph 113: When the reference data signal Vref is applied to the third electrode of the first transistor T1, the first transistor T1 may be turned on] [e.g., Yu, Paragraph 57: the current Ids entering through the sensing line 14B in the sensing period (2) is converted to an integrated value Vsen, which is a voltage value, through the integration capacitor CFB; Paragraph 49: current data is sensed from the pixels of a display panel]
during the third interval after the second interval, data signals corresponding to image data included in an active interval of a current frame are applied to the sub-pixels included in the target sub-pixel row, and [e.g., Kim, Paragraph 120: After the sampling period SMP ends, the first rewriting period RWP1 may start.; Paragraph 120: When the first rewriting period RWP1 starts, the data signal V_DATA instead of the reference data signal Vref may be applied again to the first data line DL1; Paragraph 113: the data signal V_DATA is defined as a signal applied to the first data line DL1 for light emission in the first display period DT1]
the target sub-pixel generates the driving current based on a data signal corresponding to data having a grey gradation in the pattern data. [e.g., Yu, Paragraph 74: a data voltage for a given grayscale that generates a pixel current (the source-drain current Ids of the driving TFT) greater than 0]
Kim does not expressly disclose that the data signal applied to the target row during the first interval corresponds to pattern data having a grey gradation for the target sub-pixel; Kim applies a reference data signal Vref for sensing [e.g., Kim, Paragraph 113: The reference data signal Vref is defined as a signal applied to the first data line DL1 for sensing in the first blank period BT1].
Yu discloses a sensing data voltage comprising a given-grayscale voltage for the pixels being sensed and a black-grayscale voltage for the other pixels of the same rows, applied through the data lines, with sensing performed in the vertical blank periods [e.g., Yu, Paragraph 74: The sensing data voltage comprises a data voltage for a given grayscale that generates a pixel current (the source-drain current Ids of the driving TFT) greater than 0 and a data voltage for a black gray scale that suppresses the generation of the pixel current; Paragraph 107: In the odd sensing period, the data voltage for a given grayscale is applied simultaneously to the pixels connected to the odd sensing lines through the data lines, and the data voltage for a black grayscale is applied simultaneously to the pixels connected to the even sensing lines through the data lines] [e.g., Yu, Paragraph 71: Sensing may be performed for a predetermined period of time before normal driving or for vertical blank periods during normal driving];
Yu’s pixels on the odd and even sensing lines lie in the same rows, so the two data values are distributed along each row.
The reason to combine given at claim 5 applies, and Yu’s black-grayscale data suppresses the pixel current of the pixels that are not being sensed, so that only the sensed pixel draws current on the shared sensing line during Kim’s sampling period. KSR, 550 U.S. 398; Graham, 383 U.S. 1.
Regarding claim 9, Kim and Yu further disclose: the sensing data includes electrical characteristics of the target sub-pixel. [e.g., Kim, Paragraph 53: the sensing circuit 220 may sense characteristics of elements included in one or more of the pixels PX; Paragraph 53: characteristics (e.g., a threshold voltage) thereof may be degraded] [e.g., Yu, Paragraph 79: the timing controller 11 applies a digital sensed value SD transmitted from the data driving circuit 12 to a pre-stored compensation algorithm to derive a threshold voltage variation ΔVth and a mobility variation ΔK]
Regarding claim 11, Yu further discloses the pattern data comprises a plurality of sub-data applied to the target sub-pixel row, [e.g., Yu, Paragraph 74: The sensing data voltage comprises a data voltage for a given grayscale that generates a pixel current (the source-drain current Ids of the driving TFT) greater than 0 and a data voltage for a black gray scale that suppresses the generation of the pixel current; Paragraph 107: In the odd sensing period, the data voltage for a given grayscale is applied simultaneously to the pixels connected to the odd sensing lines through the data lines, and the data voltage for a black grayscale is applied simultaneously to the pixels connected to the even sensing lines through the data lines]
each of the sub-data comprises first data having a black gradation and second data having the grey gradation, [e.g., Yu, Paragraph 74: a data voltage for a given grayscale that generates a pixel current; Paragraph 74: a data voltage for a black gray scale that suppresses the generation of the pixel current]
the first data is applied to sub-pixels other than the target sub-pixel among the sub-pixels included in the target sub-pixel row, and [e.g., Yu, Paragraph 74: if the data voltage for the given grayscale is supplied to the pixels connected to the even sensing channels, the data voltage for the black grayscale is applied to the pixels connected to the odd sensing channels]
the second data is applied to the target sub-pixel among the sub-pixels included in the target sub-pixel row. [e.g., Yu, Paragraph 107: the data voltage for a given grayscale is applied simultaneously to the pixels connected to the odd sensing lines through the data lines]
Yu applies the black-grayscale data to the pixels of the row that are not being sensed and the given-grayscale data to the pixels being sensed (¶74, ¶107). Yu senses the pixels of every other sensing line at once; with one target sub-pixel per block selected as at claim 4 (Lee’s multiplexer), the black data goes to the other sub-pixels of the row for the reason given at claim 8, so that only the target draws current on the block’s sensing line.
Regarding claim 12, Kim, Lee and Yu further disclose the first to third selection signals are applied during the second interval, and [e.g., Kim, Paragraph 118: After the first reference scan period RSP1 ends, the sampling control signal SCS may be activated; Paragraph 118: During the sampling period SMP, the sampling circuit unit 222 may receive the sensing signal through the first readout line RL1; Paragraph 113: When the reference data signal Vref is applied to the third electrode of the first transistor T1, the first transistor T1 may be turned on] [e.g., Lee, Paragraph 89: a red organic light emitting diode included in a red subpixel is sensed if SMux3 drops from logic high to logic low]
the reset signal is applied before the third interval. [e.g., Yu, Paragraph 110: in the odd sensing period, the second noise cancelling switches HOLD_EG are turned on to connect the nodes NO_O of the sampling & differential capacitors CS to the ground power source] [e.g., Kim, Paragraph 120: After the sampling period SMP ends, the first rewriting period RWP1 may start.; Fig. 8A: SMP, ADP, RWP1]
Kim’s sampling control signal SCS, and Lee’s selection signals SMux1–SMux3 in the combination of claim 4, are applied in the sampling period SMP, the second interval (¶118; ¶89). Yu turns the switch HOLD_EG on in the sensing period, after the sampled values are stored (¶110); in the frame of the combination the sensing — sampling and read-out — occupies Kim’s sampling period SMP and ADC period ADP, both of which end before the rewriting period RWP1, the third interval, starts (¶120; FIG. 8A).
The reset signal is therefore applied before the third interval in the combination; this ordering is a consequence of applying Yu’s read-out within Kim’s blank-interval sequence, and it is stated as such.
Claim 10 is rejected under 35 U.S.C. § 103 as being unpatentable over Kim in view of Lee, Yu and Le Roy as applied to claim 9 above, and further in view of Min (US 2023/0215389 A1).
Regarding claim 10, Kim, Lee, Yu and Le Roy do not expressly disclose in one frame, the target sub-pixel of each of the blocks is disposed in a different sub-pixel column.
Kim discloses that the sensed row is chosen for each frame [e.g., Kim, Paragraph 105: At least one of the plurality of driving scan signals SC1 to SCn may be randomly selected for each of the frames and may be activated during a corresponding one of the blank periods BT1 and BT2], and Yu senses the pixels of alternate columns in alternate periods [e.g., Yu, Fig. 4: P (columns), CH1, CH2 …; Paragraph 75: The odd sensing channel to which the first current integrator CI1 is connected and the even sensing channel to which the second current integrator CI2 is connected may neighbor each other]; neither places the target sub-pixel of each block in a different sub-pixel column in the same frame.
Min discloses in one frame, the target sub-pixel of each of the blocks is disposed in a different sub-pixel column. [e.g., Min, Paragraph 100: in the first scan period 1st SCAN, the first sub pixel SP1, which is any one of the sub pixels of the first pixel PX1 is sensed by the first reference voltage line RVL1. The second sub pixel SP2 which is a sub pixel having a different color from the first sub pixel SP1 of the first pixel PX1 connected to the first gate line GL1, among sub pixels of the second pixel PX2, is sensed by the second reference voltage line RVL2; Paragraph 105: during one scan period among a plurality of scan periods, sub pixels SP1, SP2, and SP3 having different colors each other may be sensed; Paragraph 102: in the second scan period 2nd SCAN, the second sub pixel SP2, which is the other one of the sub pixels of the first pixel PX1, is sensed by the first reference voltage line RVL1; Fig. 4: 1st SCAN, 2nd SCAN, 3rd SCAN, SP1–SP3, PX1–PX3]
Min’s pixels PX1, PX2 and PX3 are blocks in the sense of interpretation (b): each has its own reference voltage line RVL1, RVL2 or RVL3 through which the data driver senses its sub-pixels, that line serving as the block’s sensing line [e.g., Min, Paragraph 90: the first reference voltage line RVL1 is disposed inside the first pixel PX1, the second reference voltage line RVL2 is disposed inside the second pixel PX2, and the third reference voltage line RVL3 is disposed inside the third pixel PX3; Paragraph 99: the plurality of sub pixels SP1, SP2, and SP3 connected to the first gate line GL1 is sensed by each of the plurality of reference voltage lines RVL1, RVL2, and RVL3; Paragraph 327: a data driver configured to supply a data voltage to the N pixels via N data lines using a sensing result of the N pixels via N reference lines; Fig. 4: PX1, PX2, PX3].
In one sensing (scan) period, one sub-pixel of each block is sensed, and the sensed sub-pixel occupies a different column position in each block — SP1 in PX1, SP2 in PX2, SP3 in PX3 — with the assignment rotating in the next period [e.g., Min, Paragraph 100: in the first scan period 1st SCAN, the first sub pixel SP1, which is any one of the sub pixels of the first pixel PX1 is sensed by the first reference voltage line RVL1. The second sub pixel SP2 which is a sub pixel having a different color from the first sub pixel SP1 of the first pixel PX1 connected to the first gate line GL1, among sub pixels of the second pixel PX2, is sensed by the second reference voltage line RVL2; Paragraph 105: during one scan period among a plurality of scan periods, sub pixels SP1, SP2, and SP3 having different colors each other may be sensed; Paragraph 102: in the second scan period 2nd SCAN, the second sub pixel SP2, which is the other one of the sub pixels of the first pixel PX1, is sensed by the first reference voltage line RVL1; Fig. 4: 1st SCAN, 2nd SCAN, 3rd SCAN, SP1–SP3, PX1–PX3].
Kim, Lee, Yu, Le Roy and Min are analogous art because they are from the shared inventive field of light emitting diode display devices that sense the characteristics of sub-pixels of different colors, through a line shared by the sub-pixels of a block, during a sensing period.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to assign, in the blank-interval sensing of the combination of Kim, Lee, Yu and Le Roy, the target sub-pixel of each block to a different sub-pixel column in the same frame as Min teaches, so that one sub-pixel of every block is sensed in each sensing period and all the sub-pixels of the blocks are covered in fewer sensing periods [e.g., Min, Paragraph 107: in one scan period, three sub pixels among a plurality of sub pixels SP1, SP2, and SP3 disposed in a 9k-8th column to a 9k-th column are sensed. Therefore, only three scan periods are necessary to sense all the plurality of sub pixels SP1, SP2, and SP3 disposed in a 9k-8th column to a 9k-th column; Paragraph 106: in one scan period, only one sub pixel among a plurality of sub pixels disposed in a 9k-8th column to a 9k-th column is sensed so that nine scan periods are necessary]. KSR, 550 U.S. 398; Graham, 383 U.S. 1.
Response to Arguments
Applicant’s arguments with respect to claims 1-12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeff Piziali whose telephone number is (571)272-7678. The examiner can normally be reached Monday - Friday (7:30 AM - 4 PM).
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Jeff Piziali/
Primary Examiner, Art Unit 2628
17 September 2026
