DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 16 – 18 are allowed.
The following is an examiner’s statement of reasons for allowance: the prior art taken either singularly or in combination fails to anticipate or fairly suggest the limitations of the independent claim 16, in such a manner that a rejection under 35 U.S.C. 102 or 103 would be improper.
The prior art fails to teach a combination of all the claimed features as presented in independent claim 16 with the allowable feature being: a printed circuit board, comprising: an insulating material disposed in the through-portion, and connected to the back surface of the silicon body; and a build-up insulating layer covering at least a portion of each of the core insulating layer, the silicon capacitor, and the insulating material, and disposed in at least a portion of the through-portion, wherein a difference in coefficients of thermal expansion between the silicon body and the insulating material is smaller than at least one of a difference in coefficients of thermal expansion between the silicon body and the core insulating layer and a difference in coefficients of thermal expansion between the silicon body and the build-up insulating layer.
One close prior art Mohapatra (US 2025/0220819 A1) teaches of a printed circuit board (Fig 5), comprising: a core insulating layer (505) having a through-portion (507); a silicon capacitor (521,523; [0025-0026]) disposed in the through-portion, and including a silicon body having a front surface and a back surface and a connection pad (522) disposed on the front surface of the silicon body; an insulating material (524) disposed in the through-portion, and connected to the back surface of the silicon body; and a build-up insulating layer (511) covering at least a portion of each of the core insulating layer (505), the silicon capacitor (521,523), and the insulating material (524), and disposed in at least a portion of the through-portion; however Mohapatra does not teach wherein a difference in coefficients of thermal expansion between the silicon body and the insulating material is smaller than at least one of a difference in coefficients of thermal expansion between the silicon body and the core insulating layer and a difference in coefficients of thermal expansion between the silicon body and the build-up insulating layer.
Another close prior art Hizume (US 2019/0261513 A1) teaches of a printed circuit board (Fig 1), comprising: a core insulating layer (15) having a through-portion (15z); a silicon ([0026]) disposed in the through-portion, and including a silicon body (31) having a front surface and a back surface and a connection pad (32) disposed on the front surface of the silicon body (31); an insulating material (34) disposed in the through-portion, and connected to the back surface of the silicon body (31); and a build-up insulating layer (19) covering at least a portion of each of the core insulating layer (15), the silicon, and the insulating material (34), and disposed in at least a portion of the through-portion (15z); however Hizume does not teach a silicon capacitor and wherein a difference in coefficients of thermal expansion between the silicon body and the insulating material is smaller than at least one of a difference in coefficients of thermal expansion between the silicon body and the core insulating layer and a difference in coefficients of thermal expansion between the silicon body and the build-up insulating layer.
Therefore claims 16 – 18 are allowed.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hizume (US 2019/0261513 A1).
Regarding Claim 1, Hizume (US 2019/0261513 A1) discloses a printed circuit board (Fig 1), comprising: a first insulating layer (15; [0024]) having a through-portion (15z); a component laminate (30) including an electronic component (31) having a first surface on which a connection pad (32) is disposed and a second surface, opposite to the first surface, and an insulating material (34) disposed on the second surface of the electronic component (30), wherein at least a portion of the component laminate (30) is disposed within the through-portion (15z); and a second insulating layer (17) covering at least a portion of each of the first insulating layer (15) and the component laminate (30), and disposed in at least a portion of the through-portion (15z), wherein the insulating material (34) includes an organic insulating material ([0029] “epoxy”).
Regarding Claim 5, Hizume further discloses the printed circuit board (Fig 1) of claim 1, wherein the insulating material (34) is disposed only on the second surface (lower surface of 31) of the electronic component (30) among surfaces of the electronic component.
Claim(s) 1 – 4, 6 – 9 and 13 – 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Mohapatra (US 2025/0220819 A1).
Regarding Claim 1, Mohapatra (US 2025/0220819 A1) discloses a printed circuit board (Fig 5), comprising: a first insulating layer (505; [0048-0051]) having a through-portion (507); a component laminate (520) including an electronic component (521,523; analogous to 221,223; [0025-0027]) having a first surface on which a connection pad (522;222) is disposed and a second surface, opposite to the first surface, and an insulating material (524;224; [0028]) disposed on the second surface of the electronic component (521,523), wherein at least a portion of the component laminate (520) is disposed within the through-portion (507); and a second insulating layer (511,525; [0058]) covering at least a portion of each of the first insulating layer (505) and the component laminate (520), and disposed in at least a portion (525) of the through-portion (507), wherein the insulating material (524) includes an organic insulating material ([0028] “molding material, such as, but not limited to, an epoxy, an organic dielectric material, or the like”).
Regarding Claim 2, Mohapatra further discloses the printed circuit board (Fig 5) of claim 1, wherein the electronic component includes a silicon capacitor (Si Capacitor) ([0025-0026] “capacitor”, “silicon”).
Regarding Claim 3, Mohapatra further discloses the printed circuit board (Fig 5) of claim 1, wherein the insulating material includes an epoxy molding compound (524; [0028] “molding material, such as, but not limited to, an epoxy, an organic dielectric material, or the like”).
Regarding Claim 4, Mohapatra further discloses the printed circuit board (Fig 5) of claim 1, wherein the insulating material (524) is directly connected to the second surface of the electronic component (521,523).
Regarding Claim 6, Mohapatra further discloses the printed circuit board (Fig 5) of claim 1, wherein the first insulating layer is a single layer having a thickness of 1.2 mm or more ([0049,0057] “thickness of the glass core 505 may be between approximately 50 μm and approximately 1.4 mm”, “the core 505 may have a first thickness T1, and the layer 524 may have a second thickness T2 that is substantially equal to the first thickness T1”).
Regarding Claim 7, Mohapatra further discloses the printed circuit board (Fig 5) of claim 1, further comprising: first (506) and second wiring layers (506) respectively disposed on one surface and the other surface of the first insulating layer (505); and a first via layer (508) penetrating the first insulating layer (505), and connecting at least a portion of each of the first (506) and second (506) wiring layers to each other.
Regarding Claim 8, Mohapatra further discloses the printed circuit board (Fig 5) of claim 7, wherein at least a portion of the second insulating layer (511) is disposed on one surface of each of the first insulating layer (505) and the component laminate (23,521), to cover at least a portion of the first wiring layer (506), and at least another portion of the second insulating layer (511) is disposed on the other surface of each of the first insulating layer (505) and the component laminate, to cover at least a portion of the second wiring layer (506).
Regarding Claim 9, Mohapatra further discloses the printed circuit board (Fig 5) of claim 8, further comprising: third (513-515 at upper portion of Fig 5F) and fourth (513-515 at lower portion of Fig 5F) wiring layers respectively disposed on one surface and the other surface of the second insulating layer (511); a second via layer (513) penetrating a portion of one side of the second insulating layer, and connecting at least a portion of each of the first (506) and third (513-515) wiring layers and at least a portion of each of the first wiring layer and the connection pad (522) to each other; and a third via layer (at lower portion of Fig 5F) penetrating a portion of the other side of the second insulating layer, and connecting at least a portion of each of the second (506) and fourth (513-515) wiring layers to each other.
Regarding Claim 13, Mohapatra further discloses the printed circuit board (Fig 5) of claim 1, wherein the insulating material (524) is a material different ([0058]) from a material of the second insulating layer (511,525).
Regarding Claim 14, Mohapatra further discloses the printed circuit board (Fig 5) of claim 1, wherein a distance (see Fig 5F showing a distance between 524 and 505 is less than a thickness of 524) from the insulating material to the first insulating layer is less than a thickness (up-down distance of 524 in Fig 5F) of the insulating material (524).
Regarding Claim 15, Mohapatra further discloses the printed circuit board (Fig 5) of claim 1, wherein the insulating material (524) includes one surface (upper surface of 524) facing the electronic component (521) and another surface opposing the one surface, the another surface (lower surface of 524) of the insulating material being in contact with the second insulating layer (511).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Mohapatra (US 2025/0220819 A1) as applied to claim 9 above, and further in view of Muramatsu (US 2010/0252304 A1).
Regarding Claim 10, Mohapatra discloses the limitations of the preceding claim.
Mohapatra does not disclose the printed circuit board of claim 9, further comprising: a first resist layer disposed on one surface of the second insulating layer, and having a plurality of first openings respectively exposing at least a portion of the third wiring layer; and a second resist layer disposed on the other surface of the second insulating layer, and having a plurality of second openings respectively exposing at least a portion of the fourth wiring layer.
Muramatsu (US 2010/0252304 A1) teaches of a printed circuit board (Fig 1-2), comprising: a first resist layer (17) disposed on one surface of a second insulating layer (14), and having a plurality of first openings (at P1, 17 is open to expose P1) respectively exposing at least a portion (16) of a third wiring layer (15,16); and a second resist layer (17) disposed on another surface of the second insulating layer (14), and having a plurality of second openings (at P2) respectively exposing at least a portion (15) of a fourth wiring layer (15).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the board as disclosed by Mohapatra, further comprising: a first resist layer disposed on one surface of the second insulating layer, and having a plurality of first openings respectively exposing at least a portion of the third wiring layer; and a second resist layer disposed on the other surface of the second insulating layer, and having a plurality of second openings respectively exposing at least a portion of the fourth wiring layer as taught by Muramatsu, in order to provide protection (Muramatsu, [0046,0049]).
Regarding Claim 11, Mohapatra in view of Muramatsu teaches the limitations of the preceding claim and Muramatsu further teaches the printed circuit board (Fig 1-2) of claim 10, further comprising: a semiconductor chip (1; [0042]) disposed on one surface of the first resist layer (17), and connected to at least a portion of the exposed third wiring layer (16). Note that a chip would provide further functionality and capability to the board and furthermore to an assembly or device incorporating the board with chip.
Claim(s) 12 is rejected under 35 U.S.C. 103 as being unpatentable over Mohapatra (US 2025/0220819 A1) as applied to claim 1 above.
Regarding Claim 12, Mohapatra discloses the limitations of the preceding claim.
Mohapatra does not disclose (in Fig 5) the printed circuit board of claim 1, wherein the through-portion and the plurality of component laminate are provided in plural forms, respectively, and at least a portion of each of the component laminates is disposed in each of the through-portions.
However Mohapatra further teaches the printed circuit board (Fig 7), wherein a through-portion (707A,707B) and a plurality of component laminate (721,723 at 720A,720B) are provided in plural forms, respectively, and at least a portion of each of the component laminates is disposed in each of the through-portions (707A,707B).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the board as disclosed by Mohapatra, wherein the through-portion and the plurality of component laminate are provided in plural forms, respectively, and at least a portion of each of the component laminates is disposed in each of the through-portions as taught by Mohapatra, as both limitations are presented by the same publication and in order to increase computation capability, enable higher power, enable higher quality, enable improved performance, utilize more space and beneficially enable less routing on buildup layers (Mohapatra, [0001]), as increasing components would increase functionality of the assembly.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Choi (US 2016/0105967 A1) teaches of a printed circuit board (Fig 1), comprising: a first insulating layer (121; [0022]) having a through-portion (125); a component (150,140) laminate including an electronic component (150) having a first surface and a second surface, opposite to the first surface, and an insulating material (140) disposed on the second surface of the electronic component (150), wherein at least a portion of the component laminate (150,140) is disposed within the through-portion (125); and a second insulating layer (122) covering at least a portion of each of the first insulating layer (121) and the component laminate (150,140), and disposed in at least a portion of the through-portion (125), wherein the insulating material (140) includes an organic insulating material ([0028]). This could be used in a future 103 Rejection.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROSHN K VARGHESE/Primary Examiner, Art Unit 2847
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