DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 5 and 15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The recitation of “wherein the first transistor and the second transistor both comprise p-channel Metal-Oxide-Semiconductor (PMOS) transistors.” in claims 5 and 15 is not disclosed in the specification or shown any of the drawings.
According to Fig. 2, the first transistor in claim 2 and claim 12 is between the first sensing node SO2 and the second sensing node SO, but it is an NMOS transistor.
Both PMOS transistors should be the second transistor and the third transistor of the second precharge circuit as recited in claims 4 and 14.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are:
The connections between the first latch and the other elements of the page buffer and since the data latch is not shown in any of the drawings, it is unclear how the data latch connects to the other elements of the page buffer.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-4, 7-14 and 16-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-5, 7, 10-15 and 17-20 of U.S. Patent No. 12,229,419. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-4, 7-14 and 16-18 would have been obvious over claims 1-5, 7, 10-15 and 17-20 of the patent.
Regarding claim 1, claim 1 of the patent recites a page buffer, comprising:
a first latch;
a second latch;
a data latch; and
a dynamic latch comprising a control switch and a capacitor, wherein the capacitor and the second latch are coupled to the control switch (claim 1, lines 9-13).
It would have been obvious to one having ordinary skill in the art to recognize that the data latch is included in the page buffer to cache the data to be programmed into the memory array.
Regarding claim 2, claims 1 and 15 of the patent recite the page buffer of claim 1, further comprising:
a first precharge circuit coupled to the first latch, a first sensing node, and
a second sensing node; and
a second precharge circuit coupled to the dynamic latch (claim 1, lines 25-26) and the second sensing node (claim 1, lines 19-21),
wherein the first sensing node is coupled to a bit line, and the second sensing node is coupled to the first sensing node through a first transistor, so that the second sensing node is coupled to the bit line.
It would have been obvious to one having ordinary skill in the art to recognize that there is a transistor between a sensing node and the bit line so that the first precharge circuit is coupled to the bit line through the sensing node
Regarding claim 3, claims 10 and 11 of the patent recite the page buffer of claim 2, wherein the page buffer is configured to:
apply, through the first precharge circuit, a first voltage that is higher than a normal programming bit line voltage and lower than an inhibit bit line voltage, to the bit line corresponding to a memory cell to be subjected to a first bit line forcing operation; and
apply, through the second precharge circuit, a second voltage that is higher than the first voltage and lower than the inhibit bit line voltage, to the bit line corresponding to the memory cell to be subjected to a second bit line forcing operation.
Regarding claim 4, claims 1 and 12 of the patent recite the page buffer of claim 2, wherein the second precharge circuit comprises a second transistor and a third transistor connected in series between a supply voltage and the second sensing node, wherein a gate of the second transistor is coupled to the dynamic latch, and a gate of the third transistor is coupled to an enable signal corresponding to a second bit line forced operation.
Regarding claim 7, claim 13 of the patent recites the page buffer of claim 1, wherein the control switch comprises a single-transistor control switch or a dual-transistor control switch.
Regarding claim 8, claims 2, 3 and 14 of the patent recite the page buffer of claim 1, wherein the control switch comprises a Metal-Oxide- Semiconductor (MOS) transistor, wherein a fifth end of the MOS transistor is coupled to the second latch, and a sixth end of the MOS transistor is coupled to the capacitor.
Regarding claim 9, claims 4, 5 and 7 of the patent recite the page buffer of claim 1, wherein the first latch, the second latch, and the dynamic latch are configured to store results of three sensing operations, respectively; and
wherein the page buffer is configured to apply one voltage of four voltages to a bit line, the one voltage of four voltages being determined based on the results of the three sensing operations.
It would have been obvious to one having ordinary skill in the art to recognize that the one voltage of four voltages applied to the bit line is only a functional limitation.
Regarding claim 10, claim 17 of the patent recites a memory device, comprising:
a memory cell array comprising a memory cell string and a bit line connected to the memory cell string; and
a peripheral circuit coupled to the bit line and comprising a page buffer connected to the bit line, wherein the page buffer comprises:
a first latch;
a second latch;
a data latch; and
a dynamic latch comprising a control switch and a capacitor, wherein the capacitor and the second latch are coupled to the control switch.
It would have been obvious to one having ordinary skill in the art to recognize that the data latch is included in the page buffer to cache the data to be programmed into the memory array.
Regarding claim 11, claim 17 of the patent recites the memory device of claim 10,
wherein the first latch, the second latch, and the dynamic latch are configured to store results of three sensing operations, respectively; and
wherein the page buffer is configured to apply one voltage of four voltages to the bit line, the one voltage of four voltages being determined based on the results of the three sensing operations.
It would have been obvious to one having ordinary skill in the art to recognize that the memory device of claim 10 and the memory device of claim 17 of the patent are identical in structure; therefore, the differences between claim 11 and claim 17 of the patent are only functional limitations.
Regarding claim 12, claim 17 of the patent recites the memory device of claim 10, wherein the page buffer further comprises:
a first precharge circuit coupled to the first latch, a first sensing node, and a second sensing node; and
a second precharge circuit coupled to the dynamic latch and the second sensing node,
wherein the first sensing node is coupled to a bit line, and the second sensing node is coupled to the first sensing node through a first transistor, so that the second sensing node is coupled to the bit line.
It would have been obvious to one having ordinary skill in the art to recognize that there is a transistor between a sensing node and the bit line so that the first precharge circuit is coupled to the bit line through the sensing node
Regarding claim 13, claim 18 of the patent recites the memory device of claim 12, wherein the page buffer is configured to:
apply, through the first precharge circuit, a first voltage that is higher than a normal programming bit line voltage and lower than an inhibit bit line voltage, to the bit line corresponding to a memory cell to be subjected to a first bit line forcing operation; and
apply, through the second precharge circuit, a second voltage that is higher than the first voltage and lower than the inhibit bit line voltage, to the bit line corresponding to the memory cell to be subjected to a second bit line forcing operation.
Regarding claim 14, claims 17 and 12 of the patent recite the memory device of claim 12, wherein the second precharge circuit comprises a second transistor and a third transistor connected in series between a supply voltage and the second sensing node, wherein a gate of the second transistor is coupled to the dynamic latch, and a gate of the third transistor is coupled to an enable signal corresponding to a second bit line forced operation.
It would have been obvious to one having ordinary skill in the art to recognize that the page buffer in claim 17 is the page buffer of claim 12.
Regarding claim 16, claims 17 and 14 of the patent recite the memory device of claim 10, wherein the control switch comprises a Metal-Oxide- Semiconductor (MOS) transistor, wherein a fifth end of the MOS transistor is coupled to the second latch, and a sixth end of the MOS transistor is coupled to the capacitor.
Regarding claim 17, claims 19 and 20 of the patent recite a method of programming a memory device comprising a first latch, a second latch, a data latch, and a dynamic latch, the method comprising:
performing three sensing operations (claim 17, line 3, line 11 and line 16); and
storing three results of the three sensing operations to the first latch, the second latch, and the dynamic latch, respectively (claim 20, lines 11-12, claim 19. lines 14-15, and lines 18-19).
Regarding claim 18, claim 19 of the patent recites the method of claim 17, further comprising:
performing a first sensing operation based on a first sensing voltage;
storing first result of the first sensing operation to the second latch;
exchanging information stored in the second latch and the dynamic latch;
performing a second sensing operation based on a second sensing voltage different from the first sensing voltage;
storing second result of the second sensing operation to the second latch;
performing a third sensing operation based on a verification voltage;
storing third result of the third sensing operation to the first latch; and
exchanging information stored in the second latch and the dynamic latch.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 7, 8, 10, 12, 16 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ogawa (CN 106560897 A)
Regarding claim 1, Ogawa (Fig. 3 and Fig. 1B) shows a page buffer (PBn), comprising:
a first latch (L1);
a second latch (L2);
a data latch (buffer 50, internal control signal is used to input/output data latched in the buffer 50 and transmission of the control so as to be sent to the control circuit 11 for controlling operation.); and
a dynamic latch comprising a control switch (Fig. 3, 84) and a capacitor (70), wherein the capacitor and the second latch (L2) are coupled to the control switch (84).
Regarding claim 2, Ogawa (Fig, 3) shows the page buffer of claim 1, further comprising:
a first precharge circuit (V2 and transistors 72 and 73) coupled to the first latch (L1) a first sensing node (node of BLCLAMP and transistor 86 or 89), and a second sensing node (SNS); and
a second precharge circuit (V1 and transistor 71) coupled to the dynamic latch (84 and 70) and the second sensing node (SNS),
wherein the first sensing node is coupled to a bit line, and the second sensing node is coupled to the first sensing node through a first transistor (BLCLAMP), so that the second sensing node is coupled to the bit line.
Regarding claim 7, Ogawa (Fig. 3) shows the page buffer of claim 1, wherein the control switch (84) comprises a single-transistor control switch or a dual-transistor control switch.
Regarding claim 8, Ogawa (Fig. 3) shows the page buffer of claim 1, wherein the control switch (84) comprises a Metal-Oxide- Semiconductor (MOS) transistor, wherein a fifth end of the MOS transistor is coupled to the second latch (L2), and a sixth end of the MOS transistor is coupled to the capacitor (70).
Regarding claim 10, Ogawa (Fig. 1B and Fig. 3) claim 17 of the patent recites a memory device, comprising:
a memory cell array (Fig. 1B, 10) comprising a memory cell string and a bit line connected to the memory cell string; and
a peripheral circuit coupled to the bit line and comprising a page buffer connected to the bit line, wherein the page buffer (see the rejection of claim 1) comprises:
a first latch;
a second latch;
a data latch; and
a dynamic latch comprising a control switch and a capacitor, wherein the capacitor and the second latch are coupled to the control switch.
Regarding claim 12, Ogawa (Fig. 3 and see the rejection of claim 2) shows the memory device of claim 10, wherein the page buffer further comprises:
a first precharge circuit coupled to the first latch, a first sensing node, and a second sensing node; and
a second precharge circuit coupled to the dynamic latch and the second sensing node,
wherein the first sensing node is coupled to a bit line, and the second sensing node is coupled to the first sensing node through a first transistor, so that the second sensing node is coupled to the bit line.
Regarding claim 16, Ogawa (Fig. 3 and see the rejection of claim 8) shows the memory device of claim 10, wherein the control switch comprises a Metal-Oxide- Semiconductor (MOS) transistor, wherein a fifth end of the MOS transistor is coupled to the second latch, and a sixth end of the MOS transistor is coupled to the capacitor.
Regarding claim 17, Ogawa discloses a method of programming a memory device comprising a first latch, a second latch, a data latch, and a dynamic latch, the method comprising:
performing three sensing operations (Fig. 3, using three latch circuits L1, L2 and buffer 50); and
storing three results of the three sensing operations to the first latch, the second latch, and the dynamic latch, respectively (Fig. 3, storing the three results in L1, L2 and buffer 50).
Allowable Subject Matter
Claims 6,19 and 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Regarding claim 6, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein: a first end of the first latch is coupled to the second sensing node and a fourth transistor, a second end of the first latch is coupled to the first precharge circuit and a fifth transistor, a third end of the second latch is coupled to a sixth transistor, and a fourth end of the second latch is coupled to the control switch and a seventh transistor, wherein the second latch is coupled to the first latch through the sixth and seventh transistors, as well as the fourth and fifth transistors.” in combination with the other limitations thereof as is recited in the claim.
Regarding claim 19, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “applying an inhibit bit line voltage to a first bit line coupled to a first memory cell having a threshold voltage that higher or equal to the verification voltage based on the third result; applying a third voltage to a second bit line coupled to a second memory cell to be subjected to a second bit line forcing operation based on the second result and the third result, the third voltage equaling a second voltage minus a first voltage, the second voltage being lower than the inhibit bit line voltage, and the first voltage being lower than the second voltage; applying the first voltage to the second bit line and a third bit line coupled to a third memory cell to be subjected to a first bit line forcing operation based on the first result and the third result; and applying a normal programming bit line voltage to a fourth bit line coupled to a fourth memory cell to be subjected to a normal programming operation based on the first result, the normal programming bit line voltage being lower than the first voltage.” in combination with the other limitations thereof as is recited in the claim.
Regarding claim 20, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein the first sensing voltage is lower than the second sensing voltage, and the second sensing voltage is lower than the verification voltage.” in combination with the other limitations thereof as is recited in the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hwang (US 2015/0155012) discloses a buffer circuit of semiconductor apparatus.
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/HUAN HOANG/ Primary Examiner, Art Unit 2827
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