Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed January 17, 2025.
Status of claims to be treated in this office action:
a. Independent: 1, 10, 18
b. Pending: 1-10, 13-22
Claims 11-12 have been canceled through preliminary amendments.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings are objected to because they appear as if they were converted from grayscale to black-and-white; the lines are pixelated instead of solid black. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Regarding para. [0028] of the Detailed Description section, on p.4, make the following change:
“The calibration circuit [[220]]120 may be connected to a first external resistor RE1 via a first ZQ pin ZQ P.”
Regarding para. [0046] of the Detailed Description section, on p.7, make the following change:
“In an embodiment, the first device 100 and the second device 200 may
transmit data[[,]] based on a multi-level signal modulation technique.”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Tan et al. (US Pub. 20170237433 A1; “Tan”) in view of Haycock et al. (US Pub. 20040080338 A1; “Haycock”), and Perner et al. (US Pub. 20160217856 A1; “Perner”).
Regarding independent claim 1, Tan discloses a voltage mode driver (Fig. 3: voltage mode driver circuit; [0025] & [0033]) connected to a first node (node 310), the voltage mode driver comprising a pull-up resistor circuit (circuit comprising transistors 211 and 212, and resistors not depicted. Per [0034]: one or more passive resistors are coupled between the drain of transistor 212 and node 310 in each of the unit slice circuits in driver circuit 201, and one or more passive resistors are coupled between the drain of transistor 213 and node 310 in each of the unit slice circuits in driver circuit 201) and a pull-down resistor circuit (transistors 213 and 214, and resistors not depicted; [0034]), the pull-up resistor circuit comprising a plurality of pull-up resistors, and the pull-down resistor circuit comprising a plurality of pull-down resistors ([0034]);
a current source circuit (Fig. 2: calibration current circuit 202 and reference voltage generator circuit 203; [0023]) connected to a second node (node with “DOUT” label to the right of resistor 215) and comprising a first current source (current source circuit 231; [0041]) and a second current source (current source circuit 232; [0041]);
a pre-driver (calibration control circuit 206; [0023]) configured to control the voltage mode driver and the current source circuit ([0028]: Calibration control circuit 206 generates signals RTX for controlling the equivalent resistances of transistors 211 and 214 during the calibration mode. Calibration control circuit 206 generates signal DINB during the calibration mode. Calibration control circuit 206 also generates control signals PCDPMA, NCDPMA, LATCH, PCE, NCE, TIC, PCAL, and NCAL), based on the first data ([0068]-[0069]: FIG. 5A is a diagram that shows an example of the voltage of output signal DOUT during the calibration of n-channel transistors 214…Comparator circuit 205 compares voltage CA (i.e., DOUT) and voltage CB (i.e., VREF) to generate comparison signal COUT…In response to the logic low state in signal COUT, calibration control circuit 206 adjusts signals RTX to cause the equivalent resistance of n-channel transistors 214 to increase in each enabled unit slice circuit in driver circuit 201);
Tan does not disclose:
a device configured to transmit first data to an external device and receive second data from the external device, the device comprising:
a receiver connected to the second node and configured to obtain the second data based on a voltage level of the second node; and
a hybrid resistor connected between the first node and the second node.
However, Haycock teaches:
a device (Fig. 1: system 100; [0018]) configured to transmit first data to an external device and receive second data from the external device ([0020]: Integrated circuits 102 and 104 communicate with each other using bidirectional ports 108 and 118. Each bidirectional port sends and receives data on conductor 140), the device comprising:
a receiver (Fig. 7: differential receiver 776; [0070]) connected to the second node (positive output of driver 772) and configured to obtain the second data based on a voltage level of the second node ([0070]: Differential receiver 776 subtracts the differential voltage on conductors 753 and 755 from a differential voltage on differential data lines 775 to produce inbound data on node 777. Inbound data on node 777 represents the outbound data sent from integrated circuit 752 to integrated circuit 702 across the simultaneous bidirectional interface); and
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Haycock to Tan wherein there is a device configured to transmit first data to an external device and receive second data from the external device, and the device comprises a receiver connected to the second node and configured to obtain the second data based on a voltage level of the second node in order to implement a device that can synchronize data transmission for bidirectional data buses (Haycock, [0005]).
Also, Perner teaches:
a hybrid resistor (Fig. 7: memristive device 100; [0031]) connected between the first node (node marked with a ‘+’) and the second node (node marked with a ‘-’).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Perner to modified Tan wherein the device comprises a hybrid resistor connected between the first node and the second node in order to implement a method to perform reversable and repeatable switching between resistance states (Perner, [0014] & [0019]).
Independent claim 18 contains limitations that are substantially the same in
claimed subject matter to the limitations of independent claim 1, and is therefore rejected for the same reasons using Tan, Haycock, and Perner.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Tan (US Pub. 20170237433 A1), Haycock (US Pub. 20040080338 A1), and Perner (US Pub. 20160217856 A1) as applied to claim 1 above, and further in view of Kadoi et al. (US Pub. 20130033327 A1; “Kadoi”), Zabroda (US Pub. 20040096005 A1), and Hachiya et al. (US Pub. 20210159871 A1; “Hachiya”).
Regarding claim 2, Tan, Haycock, and Perner together disclose the limitations of claim 1. Tan discloses a calibration circuit. Neither Tan, Haycock, nor Perner discloses:
a first replica current source circuit configured to generate a first calibration current;
a first comparator having a first input terminal and a second input terminal, wherein a first reference voltage is applied to the second input terminal;
a first replica resistor circuit comprising a plurality of first replica resistors;
a first replica hybrid resistor having a first terminal and a second terminal, the first terminal being connected to the first replica resistor circuit and the first input terminal of the first comparator, and the second terminal being connected to an output terminal of the first replica current source circuit;
a second replica current source circuit configured to generate a second calibration current;
a second comparator having a first input terminal and a second input terminal, wherein the first reference voltage is applied to the second input terminal;
a second replica resistor circuit comprising a plurality of second replica resistors;
and a second replica hybrid resistor having a first terminal and a second terminal, the first terminal being connected to the second replica resistor circuit and the first input terminal of the second comparator, and the second terminal being connected to an output terminal of the second replica current source circuit.
However, Kadoi teaches:
a first replica current source circuit (Fig. 2: first element characteristic detector 101; [0022]) configured to generate a first calibration current ([0024]: first output current of the first replica transistor (1015));
a first comparator (first operational amplifier (1011); [0066]) having a first input terminal and a second input terminal, wherein a first reference voltage is applied to the second input terminal (first reference voltage VREF1; [0067]);
a first replica resistor circuit (Fig. 2: variable current source 1023; [0037]) comprising a plurality of first replica resistors (Fig. 7: plural resistors 321, 322, 323, 324, and 325; [0164]);
a second replica current source circuit (second element characteristic detector 102; [0022]) configured to generate a second calibration current ([0025]: second output current of the second replica transistor (1025));
a second comparator (second operational amplifier (1021); [0066]) having a first input terminal and a second input terminal, wherein the reference voltage is applied to the second input terminal (second reference voltage VREF2; [0070]);
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kadoi to modified Tan wherein a first replica current source circuit is configured to generate a first calibration current; a first comparator has a first input terminal and a second input terminal, wherein a first reference voltage is applied to the second input terminal; a first replica resistor circuit comprises a plurality of first replica resistors; a second replica current source circuit is configured to generate a second calibration current; and a second comparator has a first input terminal and a second input terminal, wherein the reference voltage is applied to the second input terminal in order to improve compensation accuracy in high-frequency circuits such as power amplifiers (Kadoi, [0002]).
Also, Zabroda teaches:
a first replica hybrid resistor (Fig. 15: rightmost resistor in replica of the hybrid resistor string 305; [0041]. See annotated screenshot below) having a first terminal (left side) and a second terminal (right side), the first terminal being connected to the first replica resistor circuit ([0039]: The hybrid tuner 75 contains comparator 275; [0037]: the hybrid 65 is presented in FIG. 8. The hybrid 65 contains two resistor strings 225 and 230. Examiner asserts that since Fig. 1 shows hybrid tuner 75 and hybrid 65 connected, the first terminal of the first replica hybrid resistor is connected to the first replica resistor circuit 225) and the first input terminal of the first comparator (the resistor in the string 305 is connected to a comparator because Fig. 15 itself depicts comparator 275; [0041]), and the second terminal being connected to an output terminal of the first replica current source circuit (the right side of the resistor of string 305 is connected to current source 340b; [0041]);
a second replica resistor circuit (Fig. 8: resistor string 230; [0037]) comprising a plurality of second replica resistors ([0037]);
and a second replica hybrid resistor (Fig. 15: leftmost resistor in replica of the hybrid resistor string 305; [0041]) having a first terminal (right side) and a second terminal (left side), the first terminal being connected to the second replica resistor circuit ([0039]; [0037]. Examiner asserts that since Fig. 1 shows hybrid tuner 75 and hybrid 65 connected, the first terminal of the second replica hybrid resistor is connected to the second replica resistor circuit 230) and the first input terminal of the second comparator (input node of comparator 342; [0041]), and the second terminal being connected to an output terminal of the second replica current source circuit (the right side of the resistor of string 305 is connected to current source 340a; [0041]).
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It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Zabroda to modified Tan wherein a calibration circuit comprises a first replica hybrid resistor having a first terminal and a second terminal, the first terminal being connected to the first replica resistor circuit and the first input terminal of the first comparator, and the second terminal being connected to an output terminal of the first replica current source circuit; a second replica resistor circuit comprising a plurality of second replica resistors; and a second replica hybrid resistor having a first terminal and a second terminal, the first terminal being connected to the second replica resistor circuit and the first input terminal of the second comparator, and the second terminal being connected to an output terminal of the second replica current source circuit in order to provide an adjustable compensation current to compensate for the transmitted signal at the receiver inputs (Zabroda, [0010]).
Also, Hachiya teaches:
a first comparator having a first input terminal and a second input terminal, wherein a first reference voltage is applied to the second input terminal;
a second comparator having a first input terminal and a second input terminal, wherein the first reference voltage is applied to the second input terminal (Fig. 23: comparators 24 and 44 may each receive a reference voltage Vref; [0069] & [0146]);
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Hachiya to modified Tan wherein a first comparator having a first input terminal and a second input terminal, wherein a first reference voltage is applied to the second input terminal, and a second comparator having a first input terminal and a second input terminal, wherein the first reference voltage is applied to the second input terminal in order to provide a method and device for reducing trimming errors and adjusting impedance in input and output buffers (Hachiya, [0008]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Tan (US Pub. 20170237433 A1), Haycock (US Pub. 20040080338 A1), Perner (US Pub. 20160217856 A1), Kadoi (US Pub. 20130033327 A1), Zabroda (US Pub. 20040096005 A1), and Hachiya (US Pub. 20210159871 A1) as applied to claim 2 above, and further in view of Liang (CN 111669154 A), Dent (US Pat. 5727023 A), and Hardee (US Pub. 20170179953 A1).
Regarding claim 4, Tan, Haycock, Perner, Kadoi, Zabroda, and Hachiya together disclose the limitations of claim 2. Further, through Kadoi:
second reference voltage (Fig. 2: VREF2; [0070])
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kadoi to modified Tan there is a second reference voltage in order to improve compensation accuracy in high-frequency circuits such as power amplifiers (Kadoi, [0002]).
Neither Tan, Haycock, Perner, Kadoi, Zabroda, nor Hachiya discloses:
wherein the calibration circuit further comprises a third comparator having a first input terminal and a second input terminal, wherein the first input terminal is connected to the second terminal of the first replica hybrid resistor, a reference voltage is applied to the second input terminal, and
wherein the calibration circuit is configured to calibrate the first current source and the second current source, based on a third difference between a voltage of the first input terminal of the third comparator and the reference voltage.
However, Liang teaches:
wherein the calibration circuit (Fig. 3: random delay unit; [0088]) further comprises a comparator (comparator U3) having a first input terminal and a second input terminal, wherein the first input terminal is connected to the second terminal of the first replica hybrid resistor (diffused memristor RM; [0088]), a reference voltage (VREF; [0091]) is applied to the second input terminal, and
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Liang to modified Tan wherein the calibration circuit further comprises a comparator having a first input terminal and a second input terminal, wherein the first input terminal is connected to the second terminal of the first replica hybrid resistor, a reference voltage is applied to the second input terminal in order to reduce circuit size and power consumption by using the random delay time of a diffused memristor as a random number generator (Liang, [0041]).
Also, Dent teaches:
wherein the calibration circuit (Fig. 3: speech encoder; col. 6, lines 33-34) is configured to calibrate the first current source and the second current source (Fig. 7: three parallel current sources 60, 61, and 62; col. 7, line 26), based on a third difference between a voltage of the first input terminal of the comparator (comparator 21; col. 6, lines 65-66) and the reference voltage (col. 7, lines 7-12: The sign change, up or down, is determined by the high/low decision of the comparator 21 as registered at every clock tick in the first flip-flop stage of a shift register 22. This controls whether the P or N type current source in the programmable current source 25 is enabled).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Dent to modified Tan wherein the calibration circuit is configured to calibrate the first current source and the second current source, based on a third difference between a voltage of the first input terminal of the third comparator and the reference voltage in order to implement an analog to digital converter that uses binary coded digital signals to better represent the analog signal (Dent, col. 4, lines 46-59).
Also, Hardee teaches:
a third comparator (claim 1, p.9, top of right column: a third comparator configured to compare a voltage at a third common node between the second pull-up current mirror transistor and the pull-down current source transistor to the reference voltage and to generate an output signal to drive a control terminal of the pull-down current source transistor)
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Hardee to modified Tan wherein there is a third comparator in order to provide a calibration circuit that accurately matches impedances for a range of reference voltages (Hardee, [0035]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Tan (US Pub. 20170237433 A1), Haycock (US Pub. 20040080338 A1), and Perner (US Pub. 20160217856 A1) as applied to claim 1 above, and further in view of Hietala et al. (US Pub. 20190296697 A1; “Hietala”).
Regarding claim 5, Tan, Haycock, and Perner together disclose the limitations of claim 1. Neither Tan, Haycock, nor Perner discloses:
wherein one end of the first current source is supplied with a power supply voltage, and another end of the first current source is connected to the second node, and
wherein one end of the second current source is connected to the second node, and another end of the second current source is connected to ground.
However, Hietala teaches:
wherein one end of the first current source (Fig. 3: first current source 46; [0025]) is supplied with a power supply voltage (VCC; [0022]: supply voltage node 32 labeled VCC), and another end of the first current source is connected to the second node (first reference node 48; [0025]), and
wherein one end of the second current source (third current source 80; [0029]) is connected to the second node, and another end of the second current source is connected to ground ([0029]: a third current source 80 that is coupled between the first reference node 48 and ground).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Hietala to modified Tan wherein one end of the first current source is supplied with a power supply voltage, and another end of the first current source is connected to the second node, and
wherein one end of the second current source is connected to the second node, and another end of the second current source is connected to ground in order to provide a current limiter and a voltage limiter to protect power amplifiers in phased array antenna systems (Hietala, [0004]-[0005]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Tan (US Pub. 20170237433 A1), Haycock (US Pub. 20040080338 A1), Perner (US Pub. 20160217856 A1), and Hietala (US Pub. 20190296697 A1) as applied to claim 5 above, and further in view of Seo et al. (US Pub. 20200082872 A1; “Seo”).
Regarding claim 6, Tan, Haycock, Perner, and Hietala together disclose the limitations of claim 5. Further, through Tan:
based on the first data having a first value ([0068]-[0069]. Examiner asserts that Tan teaches that circuits can be controlled by the first data),
pull-up resistor circuit (Fig. 3: 211 and 212, and resistors; [0034])
Neither Tan, Haycock, Perner, nor Hietala discloses:
wherein the pre-driver is configured to disconnect the pull-up circuit from the first node and disconnect the second current source from the second node.
However, Seo teaches:
wherein the pre-driver (Fig. 7: driving replica unit 710; [0067]) is configured to disconnect the pull-up circuit (second pull-up current source 723; [0092]) from the first node (N3) and disconnect the second current source (second pull-down current source 733; [0092]) from the second node ([0092]: The replica unit 710 may block a connection between the third connection node N3 and the second pull-up current source 723 and a connection between the fourth connection node N4 and the second pull-down current source 733 by turning off (e.g., opening) the first switch 724 and the second switch 734 in response to the switching signal SW at the logic low level).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Seo to modified Tan wherein the pre-driver is configured to disconnect the pull-up circuit from the first node and disconnect the second current source from the second node in order to implement a voltage generation circuit that generates the bit line pre-charge voltage without a dead zone (Seo, [0003]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Tan (US Pub. 20170237433 A1), Haycock (US Pub. 20040080338 A1), Perner (US Pub. 20160217856 A1), and Hietala (US Pub. 20190296697 A1) as applied to claim 5 above, and further in view of Seong et al. (WO 2024080574 A1; “Seong”).
Regarding claim 9, Tan, Haycock, Perner, and Hietala together disclose the limitations of claim 5. Further, through Tan:
based on the first data having a fourth value ([0068]-[0069]. Examiner asserts that Tan teaches that circuits can be controlled by the first data),
Neither Tan, Haycock, Perner, nor Hietala discloses:
wherein the pre-driver is configured to disconnect the pull-down resistor circuit from the first node and disconnect the first current source from the second node.
However, Seong teaches:
wherein the pre-driver (Fig. 3: 400, 500, and 600) is configured to disconnect the pull-down resistor circuit from the first node ([0087]: the impedance calibration device (1000) can turn on the pull-down enable transistor (MN31) by applying a high-level pull-down enable signal (EN_PD) to measure the resistance value of the pull-down resistor circuit (320), and connect the pull-down resistor circuit (320) to the first node (N31); [0076]: The control module (600) can connect the pull-down resistor circuit (320) to the first node (N31) by applying a pull-down enable signal (EN_PD) to the pull-down enable transistor (MN31). Examiner asserts that the pull-down enable transistor MN31 can be turned on or off, thereby connecting or disconnecting the pull-down resistor circuit) and disconnect the first current source (current source 430; [0081]) from the second node ([0081]: The control module (600) can control the connection between the current source (430) and the second node (N42) using the fourth switch (SW4)).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Seong to modified Tan wherein the pre-driver is configured to disconnect the pull-down resistor circuit from the first node and disconnect the first current source from the second node in order to provide a method for measuring and calibrating output impedance for various drivers (Seong, [0053]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Tan (US Pub. 20170237433 A1) in view of Haycock (US Pub. 20040080338 A1), Dent (US Pat. 5727023 A), Hachiya (US Pub. 20210159871 A1), Hardee (US Pub. 20170179953 A1), and Seong (WO 2024080574 A1).
Independent claim 10 contains a preamble and sixth (last) limitation that are substantially the same in claimed subject matter to the preamble and second-to-last limitation of independent claim 1, and a second limitation that is substantially the same as the second limitation of claim 4. Those limitations are therefore rejected for the same reasons using Tan, Haycock, and Dent.
Tan discloses:
adjusting based on the first data ([0068]-[0069];
Neither Tan, Haycock, nor Dent discloses:
calibrating a voltage mode driver using a calibration circuit;
adjusting a resistance value of a pull-up resistor circuit of the voltage mode driver, based on the first data;
adjusting a resistance value of a pull-down resistor circuit of the voltage mode driver, based on the first data;
adjusting a calibration current of the current source circuit,
However, Hachiya teaches:
calibrating a voltage mode driver (Fig. 23: output driver 10; [0061]) using a calibration circuit (trimming circuit 20; [0061]: The trimming circuit 20 is a circuit that adjusts an output impedance of the output driver 10 to perform impedance matching between the output driver 10 and a transmission line; [0084]: the impedances of the variable resistor elements 11 and 21a are adjusted on the basis of a comparison result, by the comparator 24, between the output voltage V21 of the replica circuit 21 and the reference voltage Vref…This makes it possible to adjust the output impedance of the output driver 10);
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Hachiya to Tan wherein a voltage mode driver is calibrated using a calibration circuit in order to provide a method and device for reducing trimming errors and adjusting impedance in input and output buffers (Hachiya, [0008]).
Also, Hardee teaches:
adjusting a resistance value of a pull-up resistor circuit (Fig. 10: pull-up circuit 150; [0042]: a pull-up circuit 150 is implemented as one or more PMOS transistors connected in parallel and then connected in series with a resistor R1 between the positive power supply voltage Vddq and an input/output node 160; [0008]: one or more resistors are placed between the PMOS transistors and the I/O node) of the voltage mode driver ([0009]: the calibration circuit calibrates a pull-up circuit unit and a pull-down circuit unit…one or more transistors within the pull-up circuit unit are turned on to set the impedance of the pull-up circuit unit to match the impedance of the off-chip resistor RZQ. In one example, a digital code is applied to the bank of PMOS transistors in the pull-up circuit unit to selectively turn on one or more of the PMOS transistors in the pull-up circuit unit to obtain the desired impedance value RZQ), based on the first data ([0010]: the logic states or bias conditions may be the digital codes used to selectively turn on one or more of the transistors in the pull-up circuit and the pull-down circuit);
adjusting a resistance value of a pull-down resistor circuit (Fig. 10: pull-down circuit 180; [0042]: A pull-down circuit 180 is implemented as one or more NMOS transistors connected in parallel and then connected in series with a resistor R2 between the input/output node 160 and the reference power supply voltage Vssq (or ground); [0008]: one or more resistors are placed between the NMOS transistors and the I/O node) of the voltage mode driver ([0009]: one or more transistors within the pull-down circuit unit are turned on to set the impedance of the pull-down circuit unit to match the impedance of the off-chip resistor RZQ. In one example, a digital code is applied to the bank of NMOS transistors in the pull-down circuit unit to selectively turn on one or more of the NMOS transistors in the pull-down circuit unit to obtain the desired impedance value RZQ), based on the first data ([0010]);
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Hardee to modified Tan wherein the calibration circuits adjusts a resistance value of a pull-up resistor circuit of the voltage mode driver based on the first data and adjusts a resistance value of a pull-down resistor circuit of the voltage mode driver based on the first data in order to provide a calibration circuit that accurately matches impedances for a range of reference voltages (Hardee, [0035]).
Also, Seong discloses:
adjusting a calibration current of the current source circuit ([0081]. Examiner asserts that connecting and disconnecting components is analogous to adjusting the value of the component between a nonzero and zero value),
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Seong to modified Tan wherein the calibration current of the current source circuit is adjusted in order to provide a method for measuring and calibrating output impedance for various drivers (Seong, [0053]).
Claims 13 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Tan (US Pub. 20170237433 A1), Haycock (US Pub. 20040080338 A1), Dent (US Pat. 5727023 A), Hachiya (US Pub. 20210159871 A1), Hardee (US Pub. 20170179953 A1), and Seong (WO 2024080574 A1) as applied to claim 10 above, and further in view of Farjadrad (US Pat. 9048934 B1) and Hietala (US Pub. 20190296697 A1).
Regarding claim 13, Tan, Haycock, Dent, Hachiya, Hardee, and Seong together disclose the limitations of claim 10. The second limitation of claim 13 is substantially the same as the limitations of claim 5, and is thus rejected for the same reasons through Hietala. Neither Tan, Haycock, Dent, Hachiya, Hardee, Seong, nor Hietala discloses:
wherein the device further comprises a hybrid resistor having one end connected to a first node and another end connected to a second node, the second node being connected to an input terminal of the receiver, and
However, Farjadrad teaches:
wherein the device (Fig. 1: transmit hybrid circuit 100;l col. 1, line 29) further comprises a hybrid resistor (a resistor from the hybrid impedance network RHr; col. 1, lines 38-39) having one end connected to a first node and another end connected to a second node, the second node being connected to an input terminal of the receiver (per Fig. 1, hybrid impedance network RHr is connected to the negative input terminal of receiver 106; col. 1, line 40), and
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Farjadrad to modified Tan wherein the device further comprises a hybrid resistor having one end connected to a first node and another end connected to a second node, the second node being connected to an input terminal of the receiver in order to implement an accurate and efficient transmit hybrid circuit (Farjadrad, col. 1, lines 56-58).
Regarding claim 17, Tan, Haycock, Dent, Hachiya, Hardee, Seong, Farjadrad, and Hietala together disclose the limitations of claim 13. Claim 17 recites substantially the same limitations as claim 9, and henceforth is rejected for the same reasons.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Tan (US Pub. 20170237433 A1), Haycock (US Pub. 20040080338 A1), Dent (US Pat. 5727023 A), Hachiya (US Pub. 20210159871 A1), Hardee (US Pub. 20170179953 A1), Seong (WO 2024080574 A1), Farjadrad (US Pat. 9048934 B1), and Hietala (US Pub. 20190296697 A1) as applied to claim 13 above, and further in view of Seo (US Pub. 20200082872 A1).
Regarding claim 14, Tan, Haycock, Dent, Hachiya, Hardee, Seong, Farjadrad, and Hietala together disclose the limitations of claim 13. Claim 14 recites substantially the same limitations as claim 6, and henceforth is rejected for the same reasons.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Tan (US Pub. 20170237433 A1), Haycock (US Pub. 20040080338 A1), and Perner (US Pub. 20160217856 A1) as applied to claim 18 above, and further in view of Seo (US Pub. 20200082872 A1) and Masaki (JP 2009152970 A).
Regarding claim 19, Tan, Haycock, and Perner together disclose the limitations of claim 18. The first limitation of claim 19 is substantially the same as the limitations of claims 6 and 14, and is thus rejected for the same reasons through Tan and Seo. Neither Tan, Haycock, Perner, nor Seo discloses:
adjust a magnitude of the current generated by the current source to three times a reference current.
However, Masaki teaches:
adjust a magnitude of the current generated by the current source to three times a reference current ([0014]: when the voltage data DO0 and DO1 are LH, the magnitude of the current is three times the reference current IB2000; [0025]: when the voltage data DI1 is at a high level (when the current value of the multi-level current data DACIN is twice or three times the reference current IB2000), and when the voltage data DI1 is at a low level (when the current value of the multi-level current data DACIN is 0 or one time the reference current IB2000)).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Masaki to modified Tan wherein the magnitude of the current generated by the current source is adjusted to three times a reference current in order to provide a signal transmission system that minimizes the impact of power supply reduction without increasing the amount of wirings (Masaki, [0033]).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Tan (US Pub. 20170237433 A1), Haycock (US Pub. 20040080338 A1), and Perner (US Pub. 20160217856 A1) as applied to claim 18 above, and further in view of Seong (WO 2024080574 A1).
Regarding claim 22, Tan, Haycock, and Perner together disclose the limitations of claim 18. Claim 22 recites substantially the same limitations as claims 9 and 17, and henceforth is rejected for the same reasons.
Allowable Subject Matter
Claims 3, 7-8, 15-16, and 20-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to
applicant's disclosure:
Chen (US Pub. 20160036417 A1): paras. [0012]-[0013] and [0036], and Figs.
1A and 6 are relevant to claims 1, 10, and 18.
Farzan et al. (US Pub. 20190394071 A1; “Farzan”): paras. [0028], [0043], [0048]-[0051], and Figs. 2 and 4A are relevant to claims 1, 10, and 18.
Guo et al. (US Pub. 20200252055 A1; “Guo”): paras. [0027], [0030] and [0049]-[0053], and Figs. 3 and 4 are relevant to claims 1, 10, and 18.
Talbot et al. (US Pat. 7135884 B1; “Talbot”): col. 6, lines 19-31, and Figs. 2 and 3 are relevant to claims 1, 10, and 18.
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/E.R.A./Examiner, Art Unit 2824
/SULTANA BEGUM/Primary Examiner, Art Unit 2824
7/25/2026
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