Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed April 3, 2025.
Status of claims to be treated in this office action:
a. Independent: 2, 12, 17
b. Pending: 2-21
Claim 1 has been canceled through preliminary amendments, and claims 2-21 are new per preliminary amendments.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign mentioned in the description: “Vs”, which is first mentioned in para. [0006] on line 15 of p.3. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Regarding para. [0019] of the Detailed Description section, make the following change:
“For example, several functional components of memory devices and/or memory systems that are well-known to those of skill in the art are not discussed in detail below (e.g., circuit components such as multiplexers and decoders, data structures such as address registers and data registers, etc.)[[.]] ”
Regarding para. [0029] of the Detailed Description section, make the following change:
“For example, host device may be a computing device such as a desktop or portable computer, a server, a hand-held device (e.g., a mobile phone, a tablet, a digital reader, a digital media player), or some component thereof (e.g., a central processing unit, a co- processor, a dedicated memory controller, etc.)[[.]]”
Regarding para. [0054] of the Detailed Description section, make the following change:
“The PLA programming operation writes LP data from the first memory cell 601 (e.g., the logic 0 programmed at time 620) to second memory cell 602, using an SLC format, in programming operation 641 (e.g., by increasing the charge stored on the charge storage structure of memory cell 602 above a threshold voltage VSLC, to states 642).[[.]]”
Appropriate correction is required.
Claim Objections
Claims 2 and 12 are objected to because of the following informalities:
Regarding claim 2, on lines 4 and 7 of the claim, make the following changes, respectively:
“initiate a first programming operation to program two or more bits”
“and before completing the first programming operation, respond to a trigger”
Regarding claim 12, on line 11 of the claim, make the following change:
“before completing the first programming operation, respond to a trigger”
Appropriate correction is required.
Claim Interpretation
Regarding independent claim 2, Examiner has interpreted “two or more bits of information at one or more first memory cells according to a first density” as meaning that each memory cell of a first group of memory cells can store two or more bits, and thus the first density must correspond to a multi-level cell format (MLC, two bits per cell) or a format with more than two bits per cell. Also, Examiner has interpreted “the two or more bits at one or more second memory cells according to a second density that is different from the first density” similarly, and thus the second density must correspond to a cell format with two or more bits per cell, but not the same format as the first density. Independent claims 12 and 17 use similar language and thus the Examiner has interpreted them similarly.
However, using a broadest reasonable interpretation of the claim language, one could conclude that for one of the two densities, two bits of information are stored in two memory cells. In other words, one of the two densities could correspond to the single-level cell format (SLC, one bit per cell). Thus, references such as Shim et al. (US Pub. 20180040368 A1; “Shim”) could be used for a 35 U.S.C. 102 rejection of claim 2. Shim teaches that the first operation or first density is SLC (paras. [0087], [0136], [0144]).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding the limitation “when the external source is restored, determine that the power loss event had previously occurred according to the previously set flag”, it is obvious that a power loss event has occurred if there is a restoration of the external source. Further, the significance of a flag being “previously set” and of a power loss event having “previously occurred” is unclear; is the claim attempting to teach two flag settings and two power loss events? The limitation also fails to teach how the controller uses the “previously set flag” to determine that a power loss event has occurred. For all these reasons, claim 9 is indefinite.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 2-4, 6-8, 12-13, and 17 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Hyun et al. (US Pub. 20150193299 A1; “Hyun”).
Regarding independent claim 2, Hyun discloses a memory device (Fig. 2: non-volatile memory system; [0010]), comprising:
a non-volatile memory (non-volatile memory device 120; [0053]) comprising a plurality of memory cells ([0060]: The non-volatile memory media 122 may comprise a plurality of cells for storing data); and
a controller (non-volatile memory media controllers 126; [0053]) configured to:
initiating a first programming operation to program two or more bits of information at one or more first memory cells according to a first density ([0246]: The controller, in one embodiment, may define which blocks are SLC and which are TLC…In one embodiment, after an erase operation, a block may be placed in SLC, MLC, and/or TLC mode…In other embodiments, for other NAND makes, or the like, the mode changes just for the current operation and then reverts back to a default mode. Examiner asserts that an erase operation is a type of programming operation which sets data to 0, so the erase operation of [0246] is analogous to a program operation. Further, Examiner asserts that this paragraph teaches that the first density for a memory block may be TLC);
and before completing the first programming operation ([0062]: the bus 127 may communicatively couple the non-volatile memory elements 123 to the non-volatile memory media controller 126 in parallel. This parallel access may allow the non-volatile memory elements 123 to be managed as a group, forming a logical memory element 129. As discussed above, the logical memory element may be partitioned into respective logical memory units (e.g., logical pages) and/or logical memory divisions (e.g., logical erase blocks). Examiner asserts that since Hyun teaches managing memory elements in parallel, it follows that operations may occur in parallel. Further, per [0096]: the non-volatile memory media 122 may require…that all three pages be programmed at the same time. Also, per [0066]: individual word lines and/or pages within an erase block may be configured and/or used as SLC storage cells, MLC storage cells, TLC storage cells, or the like, in various combinations. Examiner concludes that a second operation may be implemented on second memory cells before a first operation on first memory cells is complete), responding to a trigger by implementing a second programming operation to program the two or more bits at one or more second memory cells according to a second density that is different from the first density ([0095]: buffering the data in the non-volatile memory media 122 may protect the data from a power failure, so that the data may still be programmed after recovery from the power failure from the one or more first/source erase blocks; [0116]: the copyback module 306 is configured to minimize an amount of time between when data is stored in a first/source set of non-volatile storage cells and when the copyback module 306 copies, moves, or otherwise stores the data from the first/source set of non-volatile storage cells to a second/destination set of non-volatile storage cell; [0249]: the management module 150 may keep RBER statistics for each EB…TLC blocks, in one embodiment, may be used until their reliability falls below a threshold, or the like, then they may be demoted to SLC blocks. The TLC blocks may be demoted to MLC blocks first and then to SLC, may go directly to SLC, or the like. Examiner concludes that a power loss event or a reliability threshold is analogous to a trigger, and some TLC blocks may be changed to MLC blocks as part of a program or erase operation).
Regarding claim 3, Hyun discloses the limitations of claim 2, and further through
Hyun:
wherein the trigger is without reference to a current or impending power loss event (per the rejections of claims 1 and 12, a reliability threshold is the trigger) and corresponds to a change in an operating mode between (1) a first mode that prioritizes storage density over energy efficiency and/or speed and (2) a second mode that prioritizes the energy efficiency and/or the speed over the storage density ([0246]; [0248]: The management module 150 may determine when to switch from SLC to TLC to SLC or the like. Per [0246], Examiner asserts that “or the like” includes a switch from TLC to MLC. Also, it is known to those possessing ordinary skill in the art that TLC prioritizes storage density over energy efficiency/speed, and that MLC prioritizes energy efficiency/speed over storage density).
Regarding claim 4, Hyun discloses the limitations of claim 2, and further through
Hyun:
the first programming operation is initiated to program the two or more bits at one first memory cell according to the first density ([0246]); and
the second programming operation is implemented to program the two or more bits at two or more second memory cells according to a second density ([0096]; [0249]) that stores less bits-per-cell than the first density (known in the art; see rejection of claims 2 and 3).
Regarding claim 6, Hyun discloses the limitations of claim 4, and further through
Hyun:
the two or more bits include n bits ([0102]: with regard to FIG. 4, a single non-volatile memory element 123…may include non-volatile storage cells…that encode different numbers of bits (e.g., one or more SLC erase blocks, one or more MLC erase blocks, one or more TLC erase blocks, or the like)); and
the two or more second memory cells include n single level cells (SLCs) that are each configured to store one of the n bits ([0007]: A non-volatile memory element, in certain embodiments, comprises a set of single level cell (SLC) non-volatile memory cells).
Regarding claim 7, Hyun discloses the limitations of claim 4, and further through
Hyun:
wherein the second programming operation requires less energy and/or time to program the two or more bits than the first programming operation (per claims 2 and 3 rejections above, Hyun teaches two programming operations, and the first may be performed in a TLC mode and the second may be performed in an MLC mode. It is known to those possessing ordinary skill in the art that it is faster to program in MLC mode than in TLC mode).
Regarding claim 8, Hyun discloses the limitations of claim 4. The first two limitations of claim 8 are substantially the same as parts of the third and fourth limitations of claim 2, and are thus rejected for the same reasons. Further through
Hyun:
the non-volatile memory includes a dedicated portion configured to store data bits associated with an interrupted programming operation ([0095]: the data may still be programmed after recovery from the power failure from the one or more first/source erase blocks), wherein the one or more second memory cells are within the dedicated portion ([0097] The buffer module 302, in various embodiments, may buffer or store data in SLC storage cells for copying to TLC storage cells, in SLC storage cells for copying to MLC storage cells, in MLC storage cells for copying to TLC storage cells, or otherwise buffer or store data in a first set of storage cells for copying to a second set of storage cells with more storage states or bits per cell than the first set of storage cells. Examiner concludes that the second set of MLC memory cells may be located in the dedicated portion, which is the first/source erase blocks);
the trigger corresponds to a loss of power received from an external source that interrupts the first programming operation ([0095]);
the controller (Fig. 2: 126) is configured to:
when the external source is restored, determine that a power loss event had previously occurred ([0160]: The logical-to-physical mapping module 316, in certain embodiments, cooperates with the power-cut module 320 described below to ensure that the logical-to-physical mapping structure, logical-to-physical mappings, and associated data are accessible and recoverable after a power level for the non-volatile memory device 120 falls below a threshold (e.g., a shutdown, power-cut, restart, reboot, power loss, or the like). Examiner asserts that the power-cut module performs operations triggered by the power loss event, so the system has determined that a power loss event had occurred); and
read the two or more bits from the one or more second memory cells instead of the one or more first memory cells for a recovery operation that occurs after the power from the external source is restored ([0163]: The storage capacity recovery module 318, in one embodiment, may verify storage of the data in response to a read request for the data, in cooperation with the read module 310 servicing the read request form a second/destination set of storage cells or the like, so that the verification adds little or no overhead, since the data has already been read).
Independent claim 12 contains multiple limitations that are substantially the same in claimed subject matter as limitations of claim 1 and those limitations are rejected for the same reasons as independent claim 1. Further, “wherein the first operation is configured to iteratively add charges to one or more first memory cells to reach a targeted level representative of the two or more bits” is known to one possessing ordinary skill in the art because iteratively adding charges to reach a targeted level is the same as programming cells to a memory state, and because the first operation is written to an operation having an MLC, TLC or higher-level mode, and therefore the targeted level is representative of two or more bits. Further:
wherein the trigger is without reference to a current or impending power loss event (per the rejection above, a reliability threshold is the trigger).
Regarding claim 13, Hyun discloses all the limitations of claim 12. Claim 13
recites substantially the same limitations as claim 3, and henceforth is rejected for the
same reasons.
Independent claim 17 is nearly identical in claimed subject matter as claim 12
except for being drafted in method format instead of device format and is rejected for
the same reasons as independent claim 12.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Hyun (US Pub. 20150193299 A1) as applied to claims 2, 12, and 17 above, and further in view of Wood et al. (US Pub. 20120173827 A1; “Wood”).
Regarding claim 5, Hyun discloses the limitations of claim 4. The first two limitations of claim 5 are substantially the same as limitations from claims 2-4 and are thus rejected for the same reasons. Further, through Hyun
a change from the first operating mode to the second operating mode ([0246]; [0248]) occurring before the first programming operation completes ([0062]);
Hyun does not disclose:
the trigger is a change from the first operating mode to the second operating mode
However, Wood teaches:
the trigger is a change from the first operating mode to the second operating mode ([0075]: There may be one or more trigger events which initiate the dynamic switch between different modes (e.g., MLC, SLC using the LSB, and SLC using the MSB). Examples of some of the possible trigger events include, but are not necessarily limited to, an error count for MLC memory elements satisfying a threshold, P/E cycle count satisfying a threshold, and/or a change in storage capacity requirements (e.g., a need for more storage might trigger a switch from an SLC mode to the MLC mode). In some embodiments, a combination of trigger events may be used to initiate the dynamic switch between modes)
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Wood to Hyun wherein the trigger is a change from the first operating mode to the second operating mode in order to improve accuracy and longevity by combining MLC and SLC devices and modes (Wood, [0004]).
Regarding claim 14, Hyun discloses the limitations of claim 13. The first limitation of claim 14 is substantially the same as the first limitation of claim 5, and the second and third limitations of claim 14 are substantially the same as the limitations of claim 4. Thus, claim 14 is rejected for the same reasons as claims 4 and 5.
Regarding claim 15, Hyun and Wood together disclose the limitations of claim 14. Claim 15 recites substantially the same limitations as claim 6, and henceforth is rejected for the same reasons.
Regarding claim 16, Hyun and Wood together disclose the limitations of claim 14. Claim 16 recites substantially the same limitations as claim 7, and henceforth is rejected for the same reasons.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Hyun (US Pub. 20150193299 A1) as applied to claim 8 above, and further in view of Moore et al. (US Pub. 20160363956 A1; “Moore”).
Regarding claim 9, Hyun discloses the limitations of claim 8, and further through Hyun:
wherein the controller (Fig. 2: 126) is configured to:
response to the trigger ([0116]; [0249]); and
Hyun does not disclose:
set a flag in response to the trigger; and
when the external source is restored, determine that the power loss event had previously occurred according to the previously set flag.
However, Moore teaches:
set a flag in response to the trigger ([0075]: the interval that is committed to interval data memory on power restoration must be decommitted and then added to the relative interval that is currently active. Because time has been completely accounted for in this interval, only the PF status flag is set, the relative status flag is cleared and the interval data is committed to interval data memory at the crossing of the next real-time interval boundary; [0033]: PF: A power failure occurred during the interval. Examiner asserts that a power failure flag is set in response to the power failure); and
when the external source is restored, determine that the power loss event had previously occurred according to the previously set flag ([0075]).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Moore to modified Hyun wherein a flag is set in response to the trigger; and when the external source is restored, determine that the power loss event had previously occurred according to the previously set flag in order to record interval data when time meters fail due to a power failure (Moore, [0003]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Hyun (US Pub. 20150193299 A1) as applied to claim 8 above, and further in view of Chen et al. (US Pub. 20160253112 A1; “Chen”).
Regarding claim 10, Hyun discloses the limitations of claim 8, and further through Hyun:
the non-volatile memory (Fig. 2: 120) includes a memory block (non-volatile memory media 122; [0059]) having the one first memory cell therein ([0060]);
the controller (126) is configured to:
Hyun does not disclose:
when the external source is restored, determine that the power loss event had previously occurred in response to detecting an uncorrectable error correction code (ECC) error while reading the memory block with the one first memory cell; and
in response to determining that the power loss event had previously occurred, implement the recovery operation that includes reading the two or more bits from the two or more second memory cells within the dedicated portion.
However, Chen teaches:
when the external source is restored, determine that the power loss event had previously occurred in response to detecting an uncorrectable error correction code (ECC) error while reading the memory block with the one first memory cell ([0076]: For example, when the upper page of the ECC uncorrectable error is found out, the memory controller 20 determines that the abnormal power interruption occurs during the write operation of the upper page, and reads the data of the lower page corresponding to the upper page (corresponding to the same word line); [0061]: FIG. 3 illustrates a case where the abnormal power interruption occurs during the write operation of the data of Upper Page 1, the data read out of Upper Page 1 has the ECC uncorrectable error, and the data read out of Lower Page 1 has the ECC uncorrectable error. When it is confirmed that the data read out of Lower Page 1 has the ECC uncorrectable error…); and
in response to determining that the power loss event had previously occurred, implement the recovery operation ([0074]: the memory controller 20 also confirms whether there occurs the data destruction due to the abnormal power interruption, and determines whether the restoration process is necessary (S6)) that includes reading the two or more bits from the two or more second memory cells within the dedicated portion ([0068]: When the initialization is performed at the time of the power restoration after the abnormal power interruption, the memory controller 20 restores the written data in the area (UC). At this time, when the data is read out of each page in the uncommitted area (UC), the memory controller 20 can acquire the logical address).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Chen to modified Hyun wherein when the external source is restored, determine that the power loss event had previously occurred in response to detecting an uncorrectable error correction code (ECC) error while reading the memory block with the one first memory cell; and
in response to determining that the power loss event had previously occurred, implement the recovery operation that includes reading the two or more bits from the two or more second memory cells within the dedicated portion in order to improve write performance and restore data using non-destroyed pages (Chen, [0082]-[0083]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Hyun (US Pub. 20150193299 A1) as applied to claim 2 above, and further in view of Mylly (US Pub. 20230418523 A1).
Regarding claim 11, Hyun discloses the limitations of claim 2. The third limitation of claim 11 is substantially the same as the third limitation of claim 8, and the last two limitations of claim 11 are substantially the same as the last two limitations of claim 8, and are thus rejected for the same reasons. Further through Hyun:
wherein the controller (Fig. 2: 126) is configured to:
the one or more first memory cells ([0060]) includes one first memory cell configured to store the two or more bits ([0246]);
the one or more second memory cells includes two or more second memory cells that correspond to the second density that is different from the first density ([0095]; [0116]);
the trigger corresponds to a loss of power received from an external source that interrupts the first programming operation ([0095]);
the controller (126) is configured to:
Hyun does not disclose:
the controller includes embedded memory
However, Mylly teaches:
the controller includes embedded memory ([0063]: The embedded memory in the controller is not sufficient enough to store all the run time data needed by the module and thus some portion of the run time data is stored/mirrored in non-volatile memory (e.g. NAND) of the module. This is also necessary to avoid loss of (operation) data in case of sudden power down)
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Mylly to modified Hyun wherein the controller includes embedded memory in order to provide a memory module controller that stores operational state data to efficiently control the memory during various modes and conditions (Mylly, [0068]).
Claims 18 and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Hyun (US Pub. 20150193299 A1) as applied to claim 17 above, and further in view of Kojima et al. (US Pub. 20190212800 A1; “Kojima”).
Regarding claim 18, Hyun discloses the limitations of claim 17. The first limitation of claim 18 is substantially the same as claims 3 and 13, and is thus rejected for the same reasons. Hyun does not disclose:
wherein the one or more second programming operations are implemented directly in response to the change in the operating mode.
However, Kojima teaches:
wherein the one or more second programming operations are implemented directly in response to the change in the operating mode (claim 1: the controller: changes a mode of a write operation on first memory cells that are in an erased state, and causes the nonvolatile memory to carry out the write operation having the changed mode on the first memory cells).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Kojima to modified Hyun wherein the one or more second programming operations are implemented directly in response to the change in the operating mode in order to provide a memory system capable of writing operations despite a power loss (Kojima, [0044]).
Regarding claim 20, Hyun and Kojima together disclose the limitations of claim 18. Claim 20 recites substantially the same limitations as claim 6, and henceforth is rejected for the same reasons.
Regarding claim 21, Hyun and Kojima together disclose the limitations of claim 18. Claim 21 recites substantially the same limitations as claims 7 and 16, and henceforth is rejected for the same reasons.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Hyun (US Pub. 20150193299 A1) and Kojima (US Pub. 20190212800 A1) as applied to claim 18 above, and further in view of Wood (US Pub. 20120173827 A1).
Regarding claim 19, Hyun and Kojima together disclose the limitations of claim 18. Claim 19 recites substantially the same limitations as claim 14, and henceforth is rejected for the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Shim (US Pub. 20180040368 A1): paras. [0072], [0087], and [0111] and Figs. 12-16 are relevant to claims 2, 12, and 17.
Takeuchi et al. (US Pat. 5844841 A): col. 4, lines 26-29; col. 4, lines 1-6; and col. 32, lines 53-56; and Figs. 7-16 are relevant to claims 2, 12, and 17.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIZABETH ROSE AGGER whose telephone number is (571)270-0250. The examiner can normally be reached Mon-Fri, 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rich Elms can be reached at 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Khamdan N. Alrobaie/Primary Examiner, Art Unit 2824
/E.R.A./Examiner, Art Unit 2824
8/7/2026
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