DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO ARGUMENTS
Applicant’s arguments, see pages 9-10, filed 7/2/2026, with respect to the rejection(s) of claims 2-21 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Fuller et al. (US Pub.: 2010/0220828).
I. TERMINAL DISCLAIMER
The terminal disclaimer filed on 7/2/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of U.S. Patent No. 11,403,241; U.S. Patent No. 11,775,460; and U.S. Patent No. 12,265,489 has been reviewed and is accepted. The terminal disclaimer has been recorded.
II. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-21 are rejected under 35 U.S.C. 103 as being unpatentable over Hampel et al. (US Pub.: 2007/0260841) in view of Navid (US Pub.: 2016/0149730) and Fuller et al. (US Pub.: 2010/0220828).
As per claim 2, Hampel teaches/suggests a dynamic random access memory (DRAM) device, comprising: a plurality of interconnections (e.g. associated with interconnection between memory controller (101) and memory module (103) in Fig. 2A); one or more DRAM dies ([0002]; [0047]); and a controller (e.g. associated with memory controller (201) in Fig. 2A) coupled with the one or more DRAM dies (e.g. associated with memory module (203) in Fig. 2A) and the plurality of interconnection, the controller configured to: generate a first signal (e.g. associated with one of command/address (CA), chip-select (CS-A/CS-B), data (DQ) signaling in Fig. 2A: [0025]); generate a second signal (e.g. associated with another one of command/address (CA), chip-select (CS-A/CS-B), data (DQ) signaling in Fig. 2A: [0025]); and communicate, via the plurality of interconnect, the first signal comprising a first type of data and the second signal comprising a second type of data (e.g. associated with communicating command/address (CA) type data, chip-select (CS-A/CS-B) type data, data (DQ) type data between memory controller (201) and memory module (203) in Fig. 2A: [0025]) (Fig. 2A-2B; [0002]; [0024]-[0029]; [0031]; and [0047]-[0050]).
Hampel does not teach the device comprising:
pins;
coupled with the pins;
modulated using a first modulation scheme that includes only two levels;
modulated using a second modulation scheme that includes three or more levels; and
operating via the pins, the first signal and the second signal.
Navid teaches/suggests a dynamic random access memory (DRAM) device, comprising: pins ([0023]-[0024]); coupled with the pins ([0023]-[0024]); modulated using a first modulation scheme that includes only two levels (e.g. associated with two-level pulse amplitude modulation (PAM-2): [0014]-[0018]); modulated using a second modulation scheme that includes three or more levels (e.g. associated with four-level pulse amplitude modulation (PAM-4): [0014]-[0018]); and operating via the pins ([0023]-[0024]) (Fig. 1-3B; and [0014]-[0033]).
Fuller teaches/suggests a system comprising: communicating the first signal and the second signal (e.g. associated with data being communicated over data link using corresponding modulation and command being communicated over separate command link using a different modulation technique that data uses: [0029; [0032]-[0033]; [0043]) ([0028]-[0049])
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Navid and Fuller’s signaling into Hampel’s device for the benefit of implementing a robust multi-mode signaling system with improved eye pattern (Navid, [0015]; and [0046]-[0047]) and facilitating the determining and adjusting of offset voltage (Fuller, [0107]) to obtain the invention as specified in claim 2.
As per claim 3, Hampel, Navid and Fuller teach/suggest all the claimed features of claim 2, where Hampel, Navid and Fuller further teach/suggest the DRAM device comprising wherein the first signal is communicated concurrently with the second signal (e.g. associated with concurrent communication of command/address (CA), chip-select (CS-A/CS-B), data (DQ) signaling to carry out corresponding operations) (Hampel, claim 16; Fig. 2A-2B; [0002]; [0024]-[0029]; [0031]; [0047]-[0050]; Navid, Fig. 1-3B; [0014]-[0033]; and Fuller, [0028]-[0049]).
As per claim 4, Hampel, Navid and Fuller teach/suggest all the claimed features of claim 3, where Hampel, Navid and Fuller further teach/suggest the DRAM device comprising wherein: the first signal is communicated over a first set of pins of the plurality of pins, and the second signal is communicated over a second set of pins of the plurality of pins (Hampel, claim 16; Fig. 2A-2B; [0002]; [0024]-[0029]; [0031]; [0047]-[0050]; Navid, Fig. 1-3B; [0014]-[0033]; and Fuller, [0028]-[0049]).
As per claim 5, Hampel, Navid and Fuller teach/suggest all the claimed features of claim 2, where Hampel, Navid and Fuller further teach/suggest the DRAM device comprising wherein the controller is further configured to: generate a third signal modulated using the first modulation scheme, the third signal comprising the second type of data (Hampel, claim 16; Fig. 2A-2B; [0002]; [0024]-[0029]; [0031]; [0047]-[0050]; Navid, Fig. 1-3B; [0014]-[0033]; and Fuller, [0028]-[0049]).
As per claim 6, Hampel, Navid and Fuller teach/suggest all the claimed features of claim 5, where Hampel, Navid and Fuller further teach/suggest the DRAM device comprising wherein the controller is further configured to: configure, from among a first signaling mode associated with the first modulation scheme and a second signaling mode associated with the second modulation scheme, the second signaling mode for the second type of data, wherein the second signal is generated using the second modulation scheme based at least in part on the second signaling mode being configured for the second type of data; and configure, after configuring the second signaling mode for the second type of data, from among the first signaling mode and the second signaling mode, the first signaling mode for the second type of data, wherein the third signal is generated using the first modulation scheme based at least in part on the first signaling mode being configured for the second type of data (Hampel, claim 16; Fig. 2A-2B; [0002]; [0024]-[0029]; [0031]; [0047]-[0050]; Navid, Fig. 1-3B; [0014]-[0033]; and Fuller, [0028]-[0049]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 7, Hampel, Navid and Fuller teach/suggest all the claimed features of claim 6, where Hampel, Navid and Fuller further teach/suggest the DRAM device comprising wherein a signaling mode configured for the first type of data is fixed as the first signaling mode (Hampel, claim 16; Fig. 2A-2B; [0002]; [0024]-[0029]; [0031]; [0047]-[0050]; Navid, Fig. 1-3B; [0014]-[0033]; and Fuller, [0028]-[0049]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 8, Hampel, Navid and Fuller teach/suggest all the claimed features of claim 6, where Hampel, Navid and Fuller further teach/suggest the DRAM device comprising the second signal is communicated over a set of pins of the plurality of pins, and the third signal is subsequently communicated over the same set of pins (Hampel, claim 16; Fig. 2A-2B; [0002]; [0024]-[0029]; [0031]; [0047]-[0050]; Navid, Fig. 1-3B; [0014]-[0033]; and Fuller, [0028]-[0049]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 9, Hampel, Navid and Fuller teach/suggest all the claimed features of claim 2, where Hampel, Navid and Fuller further teach/suggest the DRAM device comprising wherein the controller is further configured to: configure, from among a first signaling mode associated with the first modulation scheme and a second signaling mode associated with the second modulation scheme, the first signaling mode for the first type of data, wherein the first signal is generated using the first modulation scheme based at least in part on the first signaling mode being configured for the first type of data; configure, after configuring the first signaling mode for the first type of data, from among the first signaling mode and the second signaling mode, the second signaling mode for the first type of data; and generate, based at least in part on configuring the second signaling mode for the first type of data, a third signal modulated using the second modulation scheme, the third signal comprising the first type of data (Hampel, claim 16; Fig. 2A-2B; [0002]; [0024]-[0029]; [0031]; [0047]-[0050]; Navid, Fig. 1-3B; [0014]-[0033]; and Fuller, [0028]-[0049]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 10, Hampel, Navid and Fuller teach/suggest all the claimed features of claim 9, where Hampel, Navid and Fuller further teach/suggest the DRAM device comprising wherein a signaling mode configured for the second type of data is fixed as the second signaling mode (Hampel, claim 16; Fig. 2A-2B; [0002]; [0024]-[0029]; [0031]; [0047]-[0050]; Navid, Fig. 1-3B; [0014]-[0033]; and Fuller, [0028]-[0049]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 11, Hampel, Navid and Fuller teach/suggest all the claimed features of claim 2, where Hampel, Navid and Fuller further teach/suggest the DRAM device comprising wherein: the first modulation scheme is a non-return-to-zero (NRZ) modulation scheme, and the second modulation scheme is a three-level pulse amplitude modulation (PAM3) scheme (Hampel, claim 16; Fig. 2A-2B; [0002]; [0024]-[0029]; [0031]; [0047]-[0050]; Navid, Fig. 1-3B; [0014]-[0033]; and Fuller, [0028]-[0049]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 12, Hampel, Navid and Fuller teach/suggest all the claimed features of claim 2, where Hampel, Navid and Fuller further teach/suggest the DRAM device comprising wherein: the first signal comprises control data, and the second signal comprises storage data (Hampel, claim 16; Fig. 2A-2B; [0002]; [0024]-[0029]; [0031]; [0047]-[0050]; Navid, Fig. 1-3B; [0014]-[0033]; and Fuller, [0028]-[0049]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 13, Hampel, Navid and Fuller teach/suggest all the claimed features of claim 2, where Hampel, Navid and Fuller further teach/suggest the DRAM device comprising wherein: the first signal comprises storage data, and the second signal comprises control data (Hampel, claim 16; Fig. 2A-2B; [0002]; [0024]-[0029]; [0031]; [0047]-[0050]; Navid, Fig. 1-3B; [0014]-[0033]; and Fuller, [0028]-[0049]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 14, Hampel, Navid and Fuller teach/suggest all the claimed features of claim 2, where Hampel, Navid and Fuller further teach/suggest the DRAM device comprising wherein: the first signal comprises control data, and the second signal comprises metadata (Hampel, claim 16; Fig. 2A-2B; [0002]; [0024]-[0029]; [0031]; [0047]-[0050]; Navid, Fig. 1-3B; [0014]-[0033]; and Fuller, [0028]-[0049]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 15, Hampel, Navid and Fuller teach/suggest all the claimed features of claim 2, where Hampel, Navid and Fuller further teach/suggest the DRAM device comprising wherein: the first signal comprises metadata, and the second signal comprises control data (Hampel, claim 16; Fig. 2A-2B; [0002]; [0024]-[0029]; [0031]; [0047]-[0050]; Navid, Fig. 1-3B; [0014]-[0033]; and Fuller, [0028]-[0049]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 16, Hampel, Navid and Fuller teach/suggest all the claimed features of claim 2, where Hampel, Navid and Fuller further teach/suggest the DRAM device comprising further comprising: a plurality of channels, wherein: the first signal is communicated over a first channel of the plurality of channels, and the second signal is communicated over a second channel of the plurality of channels (Hampel, claim 16; Fig. 2A-2B; [0002]; [0024]-[0029]; [0031]; [0047]-[0050]; Navid, Fig. 1-3B; [0014]-[0033]; and Fuller, [0028]-[0049]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 17, Hampel teaches/suggests a method comprising: generating, at one or more components of the memory system, a first signal (e.g. associated with one of command/address (CA), chip-select (CS-A/CS-B), data (DQ) signaling in Fig. 2A: [0025]); generating, by the one or more components, a second signal (e.g. associated with another one of command/address (CA), chip-select (CS-A/CS-B), data (DQ) signaling in Fig. 2A: [0025]); and communicating, from the one or more components, the first signal and the second signal, the first signal comprising a first type of data and the second signal comprising a second type of data (e.g. associated with communicating command/address (CA) type data, chip-select (CS-A/CS-B) type data, data (DQ) type data between memory controller (201) and memory module (203) in Fig. 2A: [0025]) (Fig. 2A-2B; [0002]; [0024]-[0029]; [0031]; and [0047]-[0050]).
Hampel does not teach the method comprising:
modulated using a first modulation scheme that includes only two levels;
modulated using a second modulation scheme that includes three or more levels; and
communicating the first signal and the second signal.
Navid teaches/suggests a method comprising: modulated using a first modulation scheme that includes only two levels (e.g. associated with two-level pulse amplitude modulation (PAM-2): [0014]-[0018]); modulated using a second modulation scheme that includes three or more levels (e.g. associated with four-level pulse amplitude modulation (PAM-4): [0014]-[0018]) (Fig. 1-3B; and [0014]-[0033]).
Fuller teaches/suggests a method comprising: communicating the first signal and the second signal (e.g. associated with data being communicated over data link using corresponding modulation and command being communicated over separate command link using a different modulation technique that data uses: [0029; [0032]-[0033]; [0043]) ([0028]-[0049])
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Navid and Fuller’s signaling into Hampel’s method for the benefit of implementing a robust multi-mode signaling system with improved eye pattern (Navid, [0015]; and [0046]-[0047]) and facilitating the determining and adjusting of offset voltage (Fuller, [0107]) to obtain the invention as specified in claim 17.
As per claim 18, Hampel, Navid and Fuller teach/suggest all the claimed features of claim 17, where Hampel, Navid and Fuller further teach/suggest the method comprising wherein the first signal is communicated concurrently with the second signal (Hampel, claim 16; Fig. 2A-2B; [0002]; [0024]-[0029]; [0031]; [0047]-[0050]; Navid, Fig. 1-3B; [0014]-[0033]; and Fuller, [0028]-[0049]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 19, Hampel, Navid and Fuller teach/suggest all the claimed features of claim 18, where Hampel, Navid and Fuller further teach/suggest the method comprising wherein: the first signal is communicated over a first set of pins of a plurality of pins, and the second signal is communicated over a second set of pins of the plurality of pins (Hampel, claim 16; Fig. 2A-2B; [0002]; [0024]-[0029]; [0031]; [0047]-[0050]; Navid, Fig. 1-3B; [0014]-[0033]; and Fuller, [0028]-[0049]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 20, Hampel, Navid and Fuller teach/suggest all the claimed features of claim 17, where Hampel, Navid and Fuller further teach/suggest the method further comprising: generating, by the one or more components, a third signal modulated using the first modulation scheme, the third signal comprising the second type of data (Hampel, claim 16; Fig. 2A-2B; [0002]; [0024]-[0029]; [0031]; [0047]-[0050]; Navid, Fig. 1-3B; [0014]-[0033]; and Fuller, [0028]-[0049]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references would further teach/suggest the above claimed features.
As per claim 21, Hampel, Navid and Fuller teach/suggest all the claimed features of claim 17, where Hampel, Navid and Fuller further teach/suggest the method comprising wherein: the first signal comprises one of control data, storage data, or metadata, the second signal comprises one of control data, storage data or metadata, and a type of data in the first signal is different than a type of data in the second signal (Hampel, claim 16; Fig. 2A-2B; [0002]; [0024]-[0029]; [0031]; [0047]-[0050]; Navid, Fig. 1-3B; [0014]-[0033]; and Fuller, [0028]-[0049]), wherein it would have been obvious to one of ordinary skilled in the art that the resulting combination of the references would further teach/suggest the above claimed features.
IV. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 September 07, 2026
Prosecution Insights