DETAILED ACTION
This office action is in response to the application filed on 01/07/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/01/2025 has been considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in claims 1, 9 and 13. Therefore, the “a second set of switches directly coupled to each other and to the input terminal and the output terminal” and the limitations of claims 9 and 13 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 16-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Saman US 2011/0084757.
Regarding Claim 1, Saman teaches (Figures 1-4) An apparatus (Fig. 1) comprising: a switched-capacitor circuit, comprising: an input terminal at an input voltage (Vdd); an output terminal at an output voltage (Vp); a ground terminal at a ground voltage (gnd); a first set of switches (s0-S2, s5 and S14) directly coupled to each other and to the input terminal (Vdd), and coupled to the output terminal (Outp) and configured to switch between an open state and a closed state (see fig. 2); and a second set of switches (s3-S4,s6 and s9-s10) directly coupled to each other and to the input terminal and the output terminal (Vdd and outp) and configured to switch between the open state and the closed state (See fig. 2), wherein the first set of switches and the second set of switches are configured to couple to a plurality of capacitors (C1-C2); and a controller configured to control the switched-capacitor circuit to operate the first set of switches and the second set of switches in a plurality of switching patterns to cause the input voltage to be transformed to the output voltage with different conversion ratios (See figs. 2-3, Vdd/5 and vdd/6), and wherein there are at least three states of the first set of switches and the second set of switches that transform the input voltage to the output voltage with each of the three states having the same conversion ratio (see figs. 2-3), wherein the at least three states are cycled through sequentially (phase1-phase4). (For example: Par. 27-28 and 40-51)
Regarding Claim 2, Saman teaches (Figures 1-4) wherein the at least three states (phases) are cycled through sequentially such that the conversion ratio remains the same (using fig. 2 or fig. 3). (For example: Par. 27-28 and 40-51)
Regarding Claim 3, Saman teaches (Figures 1-4) wherein the at least three states are cycled through sequentially without other states being interspersed (phases 1-4). (For example: Par. 27-28 and 40-51)
Regarding Claim 4, Saman teaches (Figures 1-4) wherein the first set of switches comprises at least three switches (s0-S2, s5 and S14) and the second set of switches comprises at least three switches (s3-S4, s6 and s9-s10).
Regarding Claim 16, Saman teaches (Figures 1-4) an apparatus (Fig. 1) comprising: a switched-capacitor circuit, comprising: a first set of switches (s0-S2, s5 and S14) directly coupled to each other and to an input terminal (Vdd) and coupled to an output terminal (Outp) and configured to alternate between an open state and a closed state (see fig. 2 or 3); and a second set of switches (s3-S4,s6 and s9-s10) directly coupled to each other and to a ground terminal (gnd), and coupled to the output terminal (Outp) and configured to alternate between the open state and the closed state (see fig. 2 or 3), wherein the first set of switches and the second set of switches are configured to connect to a plurality of capacitors (c1-c2); and a controller (controlling the switches, see fig. 4) configured to control the switched-capacitor circuit to operate the first set of switches and the second set of switches in a plurality of switching patterns (see fig. 2-3) to cause an input voltage (Vdd) at the input terminal to be transformed to an output voltage (Vp) at the output terminal, wherein over a full cycle of the plurality of switching patterns there are at least three states (phases1-4, see fig. 2 or 3) of the first set of switches and the second set of switches that transform the input voltage to the output voltage with the output voltage remaining at a substantially the same voltage (Vdd/5 or Vdd/6). (For example: Par. 27-28 and 40-51)
Regarding Claim 17, Saman teaches (Figures 1-4) wherein during the full cycle of the plurality of switching patterns (competition of the phases, see Fig. 2-3) the at least three states are cycled through sequentially such that a conversion ratio remains the same (phases 1-4, see Figs. 2-3). (For example: Par. 27-28 and 40-51)
Regarding Claim 18, Saman teaches (Figures 1-4) wherein during the full cycle (competition of the phases, see Fig. 2-3) of the plurality of switching patterns the at least three states are cycled through sequentially without other states being interspersed (phases 1-4, see Figs. 2-3). (For example: Par. 27-28 and 40-51)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-9 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saman in view of Guiliano US 2013/0094157.
Regarding Claims 5 and 19, Saman teaches (Figures 1-4) further comprising: a fourth terminal (node between S0, s5 and s6) at a constant fourth voltage (voltage at the node). (For example: Par. 27-28 and 40-51)
Saman does not teach an inductor coupled to the output terminal and to the first set of switches at the fourth terminal.
Guiliano teaches (Figure 4) an inductor (L31) coupled to the output terminal (Vo) and to the first set of switches (S31-S33) at the fourth terminal (Lx). (For example: Par. 81-83)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Saman to include an inductor coupled to the output terminal and to the first set of switches at the fourth terminal, as taught by Guiliano to filter the output signal in combination with an output capacitor.
Regarding Claims 6 and 20, Saman teaches (Figures 1-4) the first set of switches (s0-S2, s5 and S14) comprises a first switch, a second switch, and a third switch, and wherein the first switch (S1) is coupled to the input terminal and the third switch (s5) is coupled to the fourth terminal(node between S0,s5 and s6); and wherein the second set of switches (s3-S4,s6 and s9-s10) comprises a fourth switch, a fifth switch, and a sixth switch, and wherein the fourth switch is coupled to the ground terminal (s3 or s4) and the sixth switch is coupled to the fourth terminal (s6 or s9 coupled to the node between S0,s5 and s6). (For example: Par. 27-28 and 40-51)
Regarding Claim 7, Saman teaches (Figures 1-4) wherein the plurality of capacitors (c1-c2) comprise a first fly capacitor and a second fly capacitor (c1-c2).
Saman does not teach wherein the first set of switches is configured to couple to the first fly capacitor between the first switch and the second switch, and the second set of switches is configured to couple to the first fly capacitor between the fourth switch and the fifth switch; and wherein the first set of switches is configured to couple to the second fly capacitor between the second switch and the third switch, and the second set of switches is configured to couple to the second fly capacitor between the fifth switch and the sixth switch.
Guiliano teaches (Figure 4) wherein the first set of switches (s31-s33) is configured to couple to the first fly capacitor (c3a) between the first switch and the second switch (s31-s32), and the second set of switches (s34-s36) is configured to couple to the first fly capacitor between the fourth switch and the fifth switch (s35-s36); and wherein the first set of switches is configured to couple to the second fly capacitor (c3b) between the second switch and the third switch (s32-s33), and the second set of switches is configured to couple to the second fly capacitor between the fifth switch and the sixth switch (s35-s34). (For example: Par. 81-83)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Saman to include wherein the first set of switches is configured to couple to the first fly capacitor between the first switch and the second switch, and the second set of switches is configured to couple to the first fly capacitor between the fourth switch and the fifth switch; and wherein the first set of switches is configured to couple to the second fly capacitor between the second switch and the third switch, and the second set of switches is configured to couple to the second fly capacitor between the fifth switch and the sixth switch, as taught by Guiliano to carry a large amount of current without overheating..
Regarding Claim 8, Saman teaches (Figures 1-4) wherein one of the at least three states (phase 1) comprises one switch (s1) in the first set of switches and two switches (s9-s10) in the second set of switches in the closed state and remaining switches in the open state, configurable such that a current passes through one of the plurality of capacitors (C1). (For example: Par. 27-28 and 40-51)
Regarding Claim 9, Saman teaches (Figures 1-4) the circuit.
Saman does not teach wherein the one of the plurality of capacitors is in series with the inductor.
Guiliano teaches (Figure 4) wherein the one of the plurality of capacitors (c3a-c3b) is in series with the inductor (L31). (For example: Par. 81-83)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Saman to include an inductor coupled to the output terminal and to the first set of switches at the fourth terminal, as taught by Guiliano to filter the output signal in combination with an output capacitor.
Claim(s) 10-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saman in view of Guiliano US 2013/0094157 and further in view of Chun US 2009/0219078.
Regarding Claim 10, Saman teaches (Figures 1-4) a circuit.
Saman does not teach wherein one of the at least three states comprises one switch in the first set of switches and two switches in the second set of switches in the closed state and remaining switches in the open state, configurable such that a current passes through the first fly capacitor and the second fly capacitor.
Chun teaches (Figures 2-3) wherein one of the at least three states (see fig. 3c) comprises one switch (s1) in the first set of switches (s0-s2, s4 and s8) and two switches (s5 and s7 ) in the second set of switches (S3 and s5-S7) in the closed state and remaining switches in the open state, configurable such that a current passes through the first fly capacitor and the second fly capacitor (fig. 3c). (For example: Par. 17-19 and 24-41)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Saman to include wherein one of the at least three states comprises one switch in the first set of switches and two switches in the second set of switches in the closed state and remaining switches in the open state, configurable such that a current passes through the first fly capacitor and the second fly capacitor, as taught by Chun to provide a more flexible circuitry because it is capable of providing multiple output/input ratios by relatively less number of capacitors.
Regarding Claim 11, Saman teaches (Figures 1-4) wherein in the one of the at least three states (fig. 2), the first fly capacitor and the second fly capacitor are on either side of one of the first set of switches (phase 1 with c1). (For example: Par. 27-28 and 40-51)
Regarding Claim 12, Saman teaches (Figures 1-4) a circuit.
Saman does not teach wherein one of the at least three states comprises two switches in the first set of switches and one switch in the second set of switches in the closed state and remaining switches in the open state, configurable such that a current passes through one of the plurality of capacitors.
Chun teaches (Figures 2-3) wherein one of the at least three states comprises two switches (s0 and s2) in the first set of switches and one switch (s5) in the second set of switches in the closed state and remaining switches in the open state, configurable such that a current passes through one of the plurality of capacitors (c2). (For example: Par. 17-19 and 24-41)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Saman to include w wherein one of the at least three states comprises two switches in the first set of switches and one switch in the second set of switches in the closed state and remaining switches in the open state, configurable such that a current passes through one of the plurality of capacitors, as taught by Chun to provide a more flexible circuitry because it is capable of providing multiple output/input ratios by relatively less number of capacitors.
Regarding Claim 13, Saman teaches (Figures 1-4) the circuit.
Saman does not teach wherein the one of the plurality of capacitors is in series with the inductor.
Guiliano teaches (Figure 4) wherein the one of the plurality of capacitors (c3a-c3b) is in series with the inductor (L31). (For example: Par. 81-83)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Saman to include an inductor coupled to the output terminal and to the first set of switches at the fourth terminal, as taught by Guiliano to filter the output signal in combination with an output capacitor.
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saman in view of Guiliano US 2013/0094157 and further in view of Lesso US 8363856.
Regarding Claim 14, Saman teaches (Figures 1-4) the circuit.
Saman does not teach wherein one of the at least three states comprises two switches in the first set of switches and one switch in the second set of switches in the closed state and remaining switches in the open state, configurable such that a current passes through the first fly capacitor and the second fly capacitor.
Lesso teaches (Figures 9-11) wherein one of the at least three states (P1) comprises two switches (cs1 and cs2) in the first set of switches (s1-s3 and s7) and one switch (s2) in the second set of switches (s4-s6) in the closed state and remaining switches in the open state (see fig. 11), configurable such that a current passes through the first fly capacitor and the second fly capacitor (see fig. 9b). (Col. 11 lines 35-67)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Saman to include wherein one of the at least three states comprises two switches in the first set of switches and one switch in the second set of switches in the closed state and remaining switches in the open state, configurable such that a current passes through the first fly capacitor and the second fly capacitor, as taught by Lesso to avoids the need for large DC capacitors.
Regarding Claim 15, Saman teaches (Figures 1-4) wherein in the one of the at least three states (fig. 2), the first fly capacitor and the second fly capacitor are on either side of one of the first set of switches (phase 1 with c1). (For example: Par. 27-28 and 40-51)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM.
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/GUSTAVO A ROSARIO-BENITEZ/ Primary Examiner, Art Unit 2838
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