DETAILED ACTION
This action is responsive to the application filed 1/17/2025. Claims 1-20 are pending. Claims 1, 17, and 19 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on July 30, 2025. This IDS has been considered.
Drawings
The drawings are objected to because the quality of Figures 6, 8, 9, 11, 13, 14A-B, 15A-D, and 18-24 on the record, are degraded in detail because of what appears to be generation loss due to progressive photocopy distortion or the conversion from color to grey scale instead of only black and white. Applicant is advised that drawings must be black and white, and 37 C.F.R. 1.84(l) states, “All drawings must be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. Lines and strokes of different thicknesses may be used in the same drawing where different thicknesses have a different meaning.” It is noted that applicant has not submitted a color drawing petition under 37 C.F.R 1.84(a)(2) and therefore clean black and white is required.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Ferroelectric Memory Device with Multi-Bit Storage and In-Memory Arithmetic Operations.
Claim Rejections - 35 USC § 112 - Indefiniteness
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites "wherein the different capacitances of the plurality of ferroelectric capacitors increase in a direction toward higher corresponding digits of the multi-bit data". It is unclear what is meant by "increase in a direction". The specification does not clearly define or describe what "direction" refers to (e.g., a physical direction on the die, a logical ordering of the digits, a spatial arrangement of the capacitors, or some other relationship). As a result, one of ordinary skill in the art would not be able to determine the metes and bounds of the claim with reasonable certainty.
Under the broadest reasonable interpretation consistent with the specification (see MPEP 2111), and in accordance with compact prosecution as set forth in MPEP 2173.06, Claim 4 will be interpreted as requiring that the capacitances of the plurality of ferroelectric capacitors increase when moving from one capacitor to the next in correspondence with the structural sequence.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
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Claims 1, 2, 9-12, 16, 17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Dokania et al. (US 11538514; "Dokania") in view of Fan et al. ("A 3-8bit Reconfigurable Hybrid ADC Architecture with Successive-approximation and Single-slope Stages for Computing in Memory"; "Fan") and further in view of Hoya (US 20090103349).
Regarding independent claim 1, Dokania discloses a memory device comprising:
a memory cell array comprising a plurality of ferroelectric memory cells, respectively disposed at intersections of wordlines and bitlines (Fig. 6A where it illustrates an array of memory cells 601 at the intersection of word line WL0 and bit line BL0 for example.; See also col. 1, ln. 53-54; "the memory comprises ferroelectric (FE) memory bit-cell".)
wherein the charges correspond to at least one piece of multi-bit data having a plurality of digits stored in a portion of the plurality of ferroelectric memory cells that are connected to the at least one bitline (Fig. 6A where it illustrates the ferroelectric memory cell has multiple capacitors to store charge corresponding to more than a single binary digit. See also col. 3, ln. 44-47; "the memory comprises FE memory bit-cells, where an individual memory bit-cell includes 1TnC bit-cells with PLs parallel to a BL, and with individual switches coupled to the capacitors on the plate-line side").
Dokania's memory device generally uses sense amps to determine the stored value of the memory cell, and is therefore silent with respect to using an ADC to compute those values.
However, Fan teaches and an analog-to-digital converter (ADC) configured to output a digital value corresponding to charges applied through at least one bitline of the bitlines (Fig. 1 where it illustrates ADCs connected to the bit lines of the Compute-in-Memory array which generates output to an external digital processor.)
Fan, although disclosing the use of ADCs, does not specifically contemplate the selective connectivity of the bitlines to the circuit that determines the digital output of the memory device.
However, Hoya teaches selective connectivity of bit lines (para. 16; "a decoupling circuit operative to selectively connect any two of the first through fourth bit lines to the sense amp circuit".)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the ferroelectric memory device of Dokania which includes 1TnC bit-cells having multiple capacitors connected to a bitline, to incorporate the column-parallel single-slope ADC architecture taught by Fan for reading out analog signals from the memory array, and to further incorporate the selective bit line connection and decoupling technique taught by Hoya. Doing so would efficiently convert the combined charge from the multiple capacitors in the ferroelectric memory cells into a digital value using an ADC architecture while decoupling unselected bit lines to reduce interference during readout. The combination of these known techniques for memory cell structure, column-parallel ADC readout and selective bit line connection would yield no more than predictable results.
Regarding claim 2, Dokania, Fan and Hoya combined disclose the limitations of claim 1.
As applied, Dokania further discloses wherein each of the plurality of ferroelectric memory cells comprises:
a plurality of ferroelectric capacitors, each having a first end connected to a respective plate line of a plurality of plate lines (Fig. 6A where it illustrates capacitors Cfe1 – Cfen connected to plate lines PL0_1 – PL0_n respectively.);
and an access transistor having a control electrode connected to a wordline among the wordlines, a first electrode connected to a bitline among the bitlines, and a second electrode commonly connected to a second end of each of the plurality of ferroelectric capacitors (Fig 6A where it illustrates access transistor MN1 with its gate connected to word line WL0, drain connected to bit line BL0, and source connected to capacitors Cfe1 – Cfen).
Regarding claim 9, Dokania, Fan and Hoya combined disclose the limitations of claim 2.
As applied, Dokania further discloses wherein: the plurality of ferroelectric memory cells comprise a plurality of types of ferroelectric memory cells, respectively corresponding to the plurality of digits of the multi-bit data (Fig. 6A. See also Examiner's Markup above (it is noted that this limitation appears directed to Fig. 11 of the instant application). See also Spec para. 139 where it describes and defines the meaning of the phrase 'different types of ferroelectric memory cells' within the context of Fig. 11 as merely the number of plate-lines (PL0-a through PL0-d) utilized for each cell. The number of plate-lines utilized by each memory cell is considered a functional or intended-use limitation. Under MPEP § 2114(II), the manner of operating a device does not differentiate an apparatus claim from the prior art. To the extent that claim 9 requires the memory cells "comprise a plurality of types", applicant's specification recites in para. 135 that each memory cell (MC1, MC2, MC3) illustrated in Fig. 11 "may have the same structure". As seen in the Examiner's markup above, the cell structure of the instant application is identical to that of Dokania. The particular manner in which those cells are grouped into "types" or operated to represent different digits of multi-bit data does not patentably distinguish the claimed apparatus from the structure taught by Dokania).,
and the plurality of types of ferroelectric memory cells each comprise a same number of the plurality of ferroelectric capacitors, and are controlled by a different number of the plurality of plate lines depending on corresponding digits (Fig. 6A).
Regarding claim 10, Dokania, Fan and Hoya combined disclose the limitations of claim 9.
As applied, Dokania further discloses wherein, for each of the plurality of types of ferroelectric memory cells, the plurality of ferroelectric capacitors included in the ferroelectric memory cell have a same capacitance (Fig. 6A where it illustrates the ferroelectric capacitors Cfe1 through Cfen)
Regarding claim 11, Dokania, Fan and Hoya combined disclose the limitations of claim 10.
As applied, Dokania further discloses wherein: a ferroelectric memory cell corresponding to a first digit, among the plurality of digits of the multi-bit data, is controlled by a first number of the plurality of plate lines (Fig. 6A where it illustrates PL0_1 as represented in memory cell 6010,0 for example),
and a ferroelectric memory cell corresponding to a second bit having a higher digit value than the first digit, among the plurality of digits of the multi-bit data, is controlled by a second number of plurality of plate lines that is greater than the first number (Fig. 6A where it illustrates PL0_1 and PL0_2 as represented in memory cell 6010,1 for example. As noted in the rejection for claim 9 above, the specification indicates this limitation as merely the number of plate-lines (PL0-a through PL0-d) utilized for each cell. The number of plate-lines utilized by each memory cell is considered a functional or intended-use limitation. Under MPEP § 2114(II), the manner of operating a device does not differentiate an apparatus claim from the prior art. To the extent that claim 11 requires the memory cells be "controlled by a first/second number of plurality of plate lines", applicant's specification recites in para. 135 that each memory cell (MC1, MC2, MC3) illustrated in Fig. 11 "may have the same structure". As seen in the Examiner's markup above, the cell structure of the instant application is identical to that of Dokania. The particular manner in which those cells are chosen to operate a different number of plate lines does not patentably distinguish the claimed apparatus from the structure taught by Dokania) .
Regarding claim 12, Dokania, Fan and Hoya combined disclose the limitations of claim 1.
As applied, Fan further discloses further comprising: a ramp generator configured to generate a ramp voltage, wherein the ADC outputs the digital value based on the ramp voltage and a voltage corresponding to the charges (Fig. 2 where it illustrates the ramp generator as part of the ADC architecture, and Fig. 3(f) which illustrates the digital result of the final comparator based on the ramp voltage VRAMP and the charge voltage VCIM.)
Regarding claim 16, Dokania, Fan and Hoya combined disclose the limitations of claim 1.
As applied, Fan discloses an ADC used to compute the stored values of a memory device. Additionally, as applied, Hoya further discloses further comprising a plurality of switching elements disposed between the bitlines and the ADC, wherein the ADC is selectively connected to the bitlines based on an operation of the plurality of switching elements (Fig. 2 where it illustrates decoupling circuit 11. See also para. 16; "a decoupling circuit operative to selectively connect any two of the first through fourth bit lines to the sense amp circuit". As noted in the rejection for claim 1 above, Hoya's use of a sense amp to evaluate the stored values of the memory device performs the same function as the ADC in the instant application (which is also taught by Fan) and is thus is considered analogous art.).
Regarding independent claim 17, Dokania discloses a memory device comprising:
a memory cell array comprising a plurality of ferroelectric memory cells (Fig. 8A);
wherein each of the plurality of ferroelectric memory cells comprises:
an access transistor (Fig. 8A; access transistor MN1);
and a plurality of ferroelectric capacitors (Fig. 8A; Cf21-Cfen),
and wherein the plurality of ferroelectric capacitors correspond to a plurality of digits of multi-bit data, respectively (Fig 8A, memory cell 801. It is noted that this limitation appears directed to the memory cell MC1 of Figure 9 of the instant application which is substantially similar in structure to that recited by Dokania.)
Dokania's memory device generally uses sense amps to determine the stored value of the memory cell, and is therefore silent with respect to using an ADC to compute those values.
However, Fan teaches and an analog-to-digital converter (ADC) connected to the plurality of ferroelectric memory cells, the ADC being configured to output a digital value corresponding to charges applied through a bitline of the bitlines (Fig. 1 where it illustrates ADCs connected to the bit lines of the Compute-in-Memory array which generates output to an external digital processor.),
Fan, although disclosing the use of ADCs, does not specifically contemplate it being respectively and selectively connected to [the] bitlines.
However, Hoya teaches selective connectivity of bit lines (para. 16; "a decoupling circuit operative to selectively connect any two of the first through fourth bit lines to the sense amp circuit".)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the ferroelectric memory device of Dokania which includes 1TnC bit-cells having multiple capacitors connected to a bitline, to incorporate the column-parallel single-slope ADC architecture taught by Fan for reading out analog signals from the memory array, and to further incorporate the selective bit line connection and decoupling technique taught by Hoya. Doing so would efficiently convert the combined charge from the multiple capacitors in the ferroelectric memory cells into a digital value using an ADC architecture while decoupling unselected bit lines to reduce interference during readout. The combination of these known techniques for memory cell structure, column-parallel ADC readout and selective bit line connection would yield no more than predictable results.
Regarding independent claim 19, Dokania discloses a memory device comprising:
A memory cell array comprising a plurality of ferroelectric memory cells (Fig. 6A, where it illustrates memory cell 601);
wherein: the plurality of ferroelectric memory cells comprise a plurality of types of ferroelectric memory cells, respectively corresponding to a plurality of digits of multi-bit data (Fig. 6A. See also Examiner's Markup above (it is noted that this limitation appears directed to Fig. 11 of the instant application). See also Spec para. 139 where it describes and defines the meaning of the phrase 'different types of ferroelectric memory cells' within the context of Fig. 11 as merely the number of plate-lines (PL0-a through PL0-d) utilized for each cell. The number of plate-lines utilized by each memory cell is considered a functional or intended-use limitation. Under MPEP § 2114(II), the manner of operating a device does not differentiate an apparatus claim from the prior art. To the extent that claim 19 requires the memory cells "comprise a plurality of types", applicant's specification recites in para. 135 that each memory cell (MC1, MC2, MC3) illustrated in Fig. 11 "may have the same structure". As seen in the Examiner's markup above, the cell structure of the instant application is identical to that of Dokania. The particular manner in which those cells are grouped into "types" or operated to represent different digits of multi-bit data does not patentably distinguish the claimed apparatus from the structure taught by Dokania).
and the plurality of types of ferroelectric memory cells each comprise a same number of ferroelectric capacitors having a same capacitance (Fig. 6A where it illustrates that each memory cell 601 contains the same number of ferroelectric capacitors Cfe1 – Cfen),
and are controlled by a different number of plate lines depending on corresponding digits of the plurality of digits (Fig. 6A where it illustrates plate-lines PL0_1 through PL0_n in each memory cell. See also col. 3, ln. 46-47; "with PLs parallel to a BL, and with individual switches coupled to the capacitors on the plate-line side.")
Dokania's memory device generally uses sense amps to determine the stored value of the memory cell, and is therefore silent with respect to using an ADC to compute those values.
However, Fan teaches and an analog-to-digital converter (ADC) connected to the plurality of ferroelectric memory cells, the ADC being configured to output a digital value corresponding to charges applied through a bitline of the bitlines,
Fan, although disclosing the use of ADCs, does not specifically contemplate it being respectively and selectively connected to [the] bitlines.
However, Hoya teaches respective and selective connectivity of bit lines (para. 16; "a decoupling circuit operative to selectively connect any two of the first through fourth bit lines to the sense amp circuit".)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the ferroelectric memory device of Dokania which includes 1TnC bit-cells having multiple capacitors connected to a bitline, to incorporate the column-parallel ADC architecture taught by Fan for reading out analog signals from the memory array, and to further incorporate the selective bit line connection and decoupling technique taught by Hoya. Doing so would efficiently convert the combined charge from the multiple capacitors in the ferroelectric memory cells into a digital value using an ADC architecture while decoupling unselected bit lines to reduce interference during readout. The combination of these known techniques for memory cell structure, column-parallel ADC readout and selective bit line connection would yield no more than predictable results.
Regarding claim 20, Dokania, Fan and Hoya combined disclose the limitations of claim 19.
As applied, Dokania further discloses wherein:
a ferroelectric memory cell corresponding to a first digit, among the plurality of digits of the multi-bit data, is controlled by a first number of plate lines, and a ferroelectric memory cell corresponding to a second bit having a higher digit value than the first digit, among the plurality of digits of the multi-bit data, is controlled by a second number of plate lines that is greater than the first number (Fig. 6A. See also Examiner's Markup above. (it is noted that this limitation appears directed to Fig. 11 of the instant application). See also Spec para. 139 where it describes and defines the meaning of "a different number of plate lines" as being merely the number of plate lines utilized out of the four illustrated for each memory cell. The example embodiment described indicates memory cell MC1 would be controlled only with one plate line (PL0-a) out of the four, whereas memory cell MC2 would be controlled with two plate lines (PL1-a, PL1-b) out of the four. As with claim 19 above, the number of plate-lines utilized by each memory cell is considered a functional or intended-use limitation. Under MPEP § 2114(II), the manner of operating a device does not differentiate an apparatus claim from the prior art. To the extent that claim 20 requires the memory cells are "controlled by a first/second number of plate lines" (and the relationship between those numbers), applicant's specification recites in para. 135 that each memory cell (MC1, MC2, MC3) illustrated in Fig. 11 "may have the same structure". As seen in the Examiner's markup above, the cell structure of the instant application is identical to that of Dokania. The particular decision to operate some of the available plate lines for one memory cell and a different number of plate lines for a second memory cell does not patentably distinguish the claimed apparatus from the structure taught by Dokania).
Applicant is invited to redraft claims 19 and 20 (which contain functional or operational limitations) in method claim format to potentially distinguish them over prior art.
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Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Dokania et al. (US 11538514; "Dokania") in view of Fan et al. ("A 3-8bit Reconfigurable Hybrid ADC Architecture with Successive-approximation and Single-slope Stages for Computing in Memory"; "Fan"), and further in view of Hoya (US 20090103349), and further in view of Sharma et al. (US 20230180483; "Sharma").
Regarding claim 18, Dokania, Fan and Hoya combined disclose the limitations of claim 17.
As applied Dokania further discloses and the access transistor comprises:
a control electrode connected to a wordline; a first electrode connected to a bitline of the bitlines (Fig. 6A where it illustrates word line WL0 connected to the gate of the access transistor MN1, and the bit line BL0 connected to the source);
and a second electrode commonly connected to a second end of each of the plurality of ferroelectric capacitors (Fig. 6A where it illustrates storage node sn1 connected to the drain of the access transistor and the ferroelectric capacitors).
While Dokania's memory device teaches the plurality of capacitors within a given memory cell, it is silent with respect to the explicit capacitance controlled by each plate line.
However, Sharma teaches the plurality of ferroelectric capacitors have different capacitances and each have a first end connected to a corresponding plate line (Fig. 2A and 2B where it shows the various configurations of different capacitances connected to plate line PL1 for example. It is noted that this limitation appears directed to Figure 9 of the instant application. It is further noted that no specific internal structure of the capacitors themselves (such as particular plate area, electrode configuration, layer thickness or any other physical characteristics) is required, only that there are different capacitances and they are connected to the access transistor. Sharma teaches different configurations for connecting the capacitors to plate lines (see Examiner's Markup above). In one configuration (Fig. 2A for example), each capacitor symbol is coupled to its own individual plate line and represents a capacitance value of 1X. In another configuration (Fig. 2B for example), multiple capacitor symbols are coupled to an individual plate line in parallel, representing a capacitance value of 2X. Furthermore, Sharma's configuration techniques extend to N capacitor symbols (see para. 35 for example), indicating that any number of possible effective capacitance values per plate line could be realized.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the ferroelectric memory device of Dokania as modified by Fan and Hoya, to incorporate the memory unit configurations taught by Sharma, including the use of individual plate lines for respective capacitors within a memory unit. Doing so would enable different capacitances to be associated with different plate lines in the memory cells, thereby further supporting multi-bit data storage and charge-based operations, without requiring any particular physical structure of the capacitors themselves, which eases fabrication constraints. The combination applies known techniques in a routine manner to yield predictable results.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Dokania et al. (US 11538514; "Dokania") in view of Fan et al. ("A 3-8bit Reconfigurable Hybrid ADC Architecture with Successive-approximation and Single-slope Stages for Computing in Memory"; "Fan"), and further in view of Hoya (US 20090103349), and further in view of Kwak et al. (US 20200167636).
Regarding claim 13, Dokania, Fan and Hoya combined disclose the limitations of claim 12.
As applied, Fan further discloses wherein: the ramp generator generates a first ramp voltage having a first slope (pg. 3394, col. 2; "In the N-bit single-slope conversion stage, a ramp signal VRAMP is connected to the bottom plate of the last CU"),
and the ADC, outputs the digital value corresponding to an addition operation result of the first multi-bit data and the second multi-bit data based on the first ramp voltage and the first voltage (pg. 3393, col 1, sect. I; "The column-parallel ADC often uses a single-slope (SS)". See also Fig. 4 and pg. 3394, col. 2, sect II; "and the comparison result is DCMP". Note that Vcm in Figure 4 is analogous to the first voltage.)
While Fan implicitly discloses analog addition through charge summation and a ramp function to the comparator (see Fig. 3(f)), it does not explicitly disclose this function as an addition operation mode.
However, Kwak teaches in an addition operation mode (para. 21; "teachings of the present disclosure are not limited to machine learning hardware", "that involve arithmetic operations, such as additions"),
receives a first voltage based on charges corresponding to first multi-bit data and second multi-bit data (Fig. 3. See also para 44; " each output 350, 352 may result from the summation of zero, one, or two currents"),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the ferroelectric memory device of Dokania as modified by Fan and Hoya, to further incorporate the teachings of Kwak regarding performing analog addition of computation results prior to digitization. Doing so would enable an addition operation mode in which charges corresponding to the first and second multi-bit data are combined on the bit lines (either through the switching circuit taught by Hoya or by multiple cells discharging on to one shared bit line as taught by Dokania), and the resulting summed analog value is efficiently converted to a digital representation using the single-slope ADC of Fan. The combination of these known elements and techniques would have yielded predictable results.
Claims 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Dokania et al. (US 11538514; "Dokania") in view of Fan et al. ("A 3-8bit Reconfigurable Hybrid ADC Architecture with Successive-approximation and Single-slope Stages for Computing in Memory"; "Fan"), and further in view of Hoya (US 20090103349), and further in view of Ocker (US 20220139437).
Regarding claim 3, Dokania, Fan and Hoya combined disclose the limitations of claim 2.
As applied, Dokania further discloses wherein the plurality of ferroelectric capacitors correspond to respective digits of multi-bit data (Fig. 6A where it illustrates a 1TnC memory cell with capacitors Cfe1 – Cfen. It is noted that Donkania1's 1TnC memory cell is structurally identical to that of the instant application. Additionally, it is well understood in the art that all 1TnC memory cells of this structure are "multi-bit" by definition as each of the capacitors independently hold a polarization state, which when combined on the common storage node, may represent more than two values (e.g., one bit = two values).
Dokania, Fan and Hoya combined are silent with respect to the explicit capacitance value of the ferroelectric capacitors.
However, Ocker teaches wherein the plurality of ferroelectric capacitors have different capacitances (Fig. 5F where it illustrates the first ferroelectric capacitor with a height of h(24) and the second ferroelectric capacitor with a height of h(44) which are different and therefore correspond to different capacitances.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the ferroelectric memory device of Dokania as modified by Fan and Hoya, to further incorporate the teachings of Ocker regarding different capacitance values for the plurality of ferroelectric capacitors in the memory cell. Doing so would enable a larger range of stored values per memory cell.
Regarding claim 4, notwithstanding the rejection for indefiniteness above, Dokania, Fan, Hoya and Ocker combined disclose the limitations of claim 3.
As applied, Ocker further discloses wherein the different capacitances of the plurality of ferroelectric capacitors increase in a direction toward higher corresponding digits of the multi-bit data (Fig. 3A where it illustrates the first capacitor with height h(24) and a next capacitor (in sequence) having a height of h(44). See also para. 62; "the capacitive memory structure 2 may have a first capacitance and the capacitive structure may have a second capacitance different from the first capacitance").
Regarding claim 5, Dokania, Fan and Hoya combined disclose the limitations of claim 2.
Dokania, Fan and Hoya combined are silent with respect to specific physical cylindrical capacitor structures or layouts.
However, Ocker teaches wherein the plurality of ferroelectric capacitors comprise:
a cylindrical inner electrode (Fig. 5F where it illustrates electrode pillar 12. See also para. 51; "the electrode pillar 12 may have a cylindrical shape, such as a circular cylindrical shape");
a ferroelectric layer surrounding an outer peripheral surface of the cylindrical inner electrode (Fig. 5A where it illustrates memory material portion 22. See also para. 53; "a memory material, such as any kind of spontaneous-polarizable material (e.g., a ferroelectric memory material)")
and a plurality of outer electrodes surrounding an outer peripheral surface of the ferroelectric layer, the plurality of outer electrodes corresponding respectively to the plurality of ferroelectric capacitors (Fig. 5F where it illustrates outer first electrode 24 and second electrode 44 for example),
and wherein the plurality of outer electrodes have different heights and are separated from each other in an axial direction (Fig. 5F where it illustrates the first electrode having height h(24) and the second electrode having height h(44) and which are separated in the axial direction. See also para. 61; "a height h(24) of the first electrode layer 24 (e.g., defined in z-direction) may be different from a height h(44) of the second electrode layer 44").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the ferroelectric memory device of Dokania as modified by Fan and Hoya, to further incorporate the teachings of Ocker regarding physical configuration of cylindrical ferroelectric capacitors. Doing so would provide a compact, vertically integrated capacitor structure that allows for tunable or differentiated capacitances through variation in electrode height, while maintaining compatibility with the bit line discharge and readout architecture already taught by Dokania, in view of Fan and Hoya.
Regarding claim 6, Dokania, Fan, Hoya and Ocker combined disclose the limitations of claim 5.
As applied, Ocker further discloses wherein: the cylindrical inner electrode (Fig. 5F, inner electrode 12)
Ocker discloses a similar 1TnC memory cell utilizing cylindrical ferroelectric capacitors, but is silent with respect to connecting the inner electrode of the capacitor to a source/drain terminal of the access transistor.
However, as applied, Dokania further discloses is connected to the second electrode of the access transistor (Fig. 4B where it illustrates the inner electrode of capacitor 400 (see Fig. 4A) connected to the source 302 of the access transistor MN of the 1TnC memory cell 420),
and the plurality of outer electrodes are connected to the plurality of plate lines, respectively (Fig. 4B where it illustrates plate line PL connected to the outer electrode of capacitor 400. While only one example capacitor is shown in Fig. 4B for clarity, Dokania discloses further embodiments (such as Fig. 6A for example) which demonstrate any number of FE capacitors connected to the source of the access transistor).
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Dokania et al. (US 11538514; "Dokania") in view of Fan et al. ("A 3-8bit Reconfigurable Hybrid ADC Architecture with Successive-approximation and Single-slope Stages for Computing in Memory"; "Fan"), and further in view of Hoya (US 20090103349), and further in view of Novozhilov et al. ("Epitaxial ferroelectric capacitors obtained by MOCVD").
Regarding claim 7, Dokania, Fan and Hoya combined disclose the limitations of claim 2.
As applied, Dokania further discloses wherein the plurality of ferroelectric capacitors comprise:
a first planar electrode (col. 8, ln. 20-22; "The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor);
a ferroelectric layer stacked on the first planar electrode (Fig. 3A. See also col. 8, ln. 18-20; "a memory is provided which comprises a capacitor including non-linear polar material");
Dokania discloses multiple planar FE capacitors connected to the storage node, but is silent with respect to them explicitly sharing one contiguous physical layer for the first electrode.
However, Novozhilov teaches and a plurality of second planar electrodes stacked on the ferroelectric layer and respectively corresponding to the plurality of ferroelectric capacitors (Fig. 8. See also pg. 635 sect 3.3.1; "For ferroelectric measurements on each wafer we formed series of capacitors with common bottom electrode and separate top electrode plates (200 to 200 rnkm2) by standard photolithography. SEM image of patterned top electrode is shown in Fig 8.,
and wherein the plurality of second planar electrodes have different widths and are separated from each other (Fig. 8 where it illustrates the top electrode layers are separated. It is well understood in the art that the capacitance of a parallel-plate capacitor is directly proportional to the area of the plates. Varying the widths of the second planar electrode to achieve different capacitances would amount to no more than a routine engineering design choice or optimization yielding expected component values.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the ferroelectric memory device of Dokania as modified by Fan and Hoya, to further incorporate the teachings of multiple top electrodes sharing a common bottom electrode, as taught by Novozhilov. Doing so is a known and conventional technique for fabricating multiple ferroelectric capacitors on the same substrate while sharing a common electrode, thereby simplifying fabrication and improving device density.
Regarding claim 8, Dokania, Fan, Hoya, and Novozhilov combined disclose the limitations of claim 7.
As applied, Dokania further discloses wherein: the first planar electrode is connected to the second electrode of the access transistor (Fig. 6A where it illustrates the first electrode of capacitors Cfe1-Cfen connected to the source of the access transistor),
and the plurality of second planar electrodes are connected to the plurality of plate lines, respectively (Fig. 6A where it illustrates the second electrode of capacitors Cfe1-Cfen connected to plate lines PL0_1-PL0_n respectively).
Allowable Subject Matter
Claims 14 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 14, the prior art teaches the limitations of claim 12. It is silent with respect to the ramp generator generates a second ramp voltage having a second slope based on the digital value, output by the ADC and corresponding to first multi-bit data, in a multiplication operation mode, and the ADC, when receiving a second voltage based on charges corresponding to second multi-bit data, outputs the digital value corresponding to the first multi-bit data and the second multi-bit data based on the second ramp voltage and the second voltage in the multiplication operation mode.
Conclusion
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/James S. Wells/Examiner, Art Unit 2825 /Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825
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