DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim7, 14 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
The claim 7, 14 are not matching to what is in the Fig. 3 of the spec of the instant application:
Claim 7 recites “7. The memory device of claim 1, wherein the control logic includes: a first inverter configured to receive a master signal and a first power supply voltage; and a first transistor configured to receive a power supply voltage, and wherein the first transistor is configured to, based on a level of the first power supply voltage being higher than a level of the power supply voltage, be turned on and output the master enable signal.”:
while in the Fig. 3, when “MASTER” signal is at high, the gate of 302 will be at ground level, the 302 will be on, regardless VDD vs VDD1, since 302 is a PFET type transistor as shown in the Fig. 3; if 302 is intended to be a NFET, a proper change of Fig. 3 is required; in [0052] 302 is a PFET, and may be a NFET is noted.
if the 302 is NFET, the claim 7 statement is true as long as VDD1 is high enough to turn on the 302 when “MASTER” is at low.
Claim 14 has a similar issue.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 8-13, 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fackenthal et al. (PGPUB 20200401490), hereinafter as Fackenthal.
Regarding claim 1, Fackenthal teaches a memory device comprising: a memory cell array including a first memory bank and a second memory bank (Fig 1, different memory dies);
a control logic (Fig 6, control circuit 605) configured to control operations of the memory cell array and generate a master enable signal and a master disable signal (Fig 6, signal controls on/off of 620);
a first repair circuit (Fig 6, repair circuit 615-a…) configured to perform a repair operation on memory cells of the first memory bank; and
a second repair circuit configured to perform the repair operation on memory cells of the second memory bank (Mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.),
wherein the first repair circuit is configured to operate based on the control logic generating the master enable signal in a normal mode ([0108] If the enable bit is asserted, the switching component 620 may activate, thereby establishing a conductive path between the power supply and 625 and the repair circuits 615, and it is obvious that when a device is operating, it is in a mode), and
wherein the control logic is configured to block a first current to the second repair circuit based on the master disable signal in the normal mode ([0108] If the enable bit is not asserted, the switching component 620 may deactivate, thereby isolating the power supply 625 from the repair circuits 615).
Regarding claim 2, Fackenthal teaches the master disable signal is configured to block a power supply voltage supplied to the second repair circuit (Fig 6).
Regarding claim 3, Fackenthal teaches the first repair circuit includes: a fuse circuit storing a fail address showing fail characteristics in the memory cell array ([0069] address … obtained from fuse);
a content-addressable memory (CAM) cell configured to compare an address with the fail address and output hit signals; and a combinational logic circuit (Fig 6, circuit output the control signal for 620) configured to output a repair enable signal, based on the hit signals, wherein the CAM cell includes:
a fail address memory (Fig 4, latch 420) including a first register storing a first address and a second register (Fig 5, fuses storing Incoming Address) storing a second address; and an address comparator circuit (Fig 4, 425a…) configured to respectively compare address bit values stored in the first register with address bit values stored in the second register and configured to output the hit signals (Fig 4, Match signal).
Regarding claim 4, Fackenthal teaches each of the first register and the second register includes one of a static random-access memory (SRAM) cell and a dual interlocked storage cell SRAM cell (the examiner is taking note that it is well known in the field a latch circuit/register circuit is a SRAM cell or a dual interlocked SRAM cell).
Regarding claim 5, Fackenthal teaches the address comparator circuit is configured to output the hit signals by using XNOR logic circuits, wherein the address bit values from the first register and the address bit values from the second register are respectively input into the XNOR logic circuits (Fig 4).
Regarding claim 6, Fackenthal teaches in the repair enable signal is configured to be at a high logic level when the first address matches the second address, and the repair enable signal is configured to be at a low logic level when the first address does not match the second address (Fig 4, XOR outputs is high when two are not matched, and it is known in the field to adding an inverter to make the logic value as needed).
Regarding claim 8, Fackenthal teaches a memory device comprising: a memory cell array including a plurality of memory cells;
a control logic configured to control operations of the memory cell array and generate a master enable signal and a master disable signal (Fig 6, signal controls on/off of 620); and
a first circuit configured to perform a first operation on the plurality of memory cells, wherein, based on the first circuit operating as a repair circuit, the first circuit is configured to operate based on the master enable signal in a normal mode, and the control logic is configured to block a first current to the first circuit based on the master disable signal in the normal mode (Fig 6, and [0108], and it is obvious that when a device is operating, it is in a mode.).
Regarding claim 9, Fackenthal teaches the master disable signal is configured to block a power supply voltage supplied to the first circuit (Fig 6).
Regarding claim 10, Fackenthal teaches the first circuit corresponds to one of the repair circuit or a test circuit (Fig 6).
Regarding claim 11, argument used in rejection of claim 3 applies.
Regarding claim 12, argument used in rejection of claim 4 applies.
Regarding claim 13, arguments used in rejection of claim 5 and 6 applies.
Regarding claim 15, Fackenthal teaches when the memory device is operating in the normal mode, wherein, when the first circuit corresponds to the repair circuit, the first circuit is configured to perform a repair operation, based on the master enable signal, and is configured to not perform the repair operation, based on the master disable signal (argument used in rejection of claim 8 applies), and wherein, when the first circuit corresponds to the test circuit, the first circuit is configured to perform a test operation, based on the master enable signal, and is configured to not perform the test operation, based on the master disable signal (Mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8., a test operation here is treated just as another operation).
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fackenthal, in view of Kim (PGPUB 20170011780), hereinafter as Kim.
Regarding claim 16, Fackenthal teaches an operating method of a memory device, the operating method comprising:
applying a power supply voltage to the memory device according to power-on of the memory device (the examiner is taking note it is a well known fact);
generating and outputting a master enable signal and a master disable signal, based on the power supply voltage;
performing a repair operation based on a control logic generating the master enable signal in a normal mode ([0108]); and
not performing the repair operation based on the control logic generating the master disable signal based on the memory device operating in the normal mode ([0108] argument used in rejection of claim 1 applies),
but not expressly generating and outputting a master enable signal and a master disable signal, based on the power supply voltage;
Kim teaches generating and outputting a master enable signal and a master disable signal, based on the power supply voltage ([0011]).
Since Kim and Fackenthal are both from the same field of semiconductor memory device, the purpose disclosed by Kim would have been recognized in the pertinent art of Fackenthal.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use voltage detecting device as in Kim into the device of Fackenthal for the purpose of controlling an operation based on levels of the supply voltage.
Regarding claim 17, argument used in rejection of claim 3 applies.
Regarding claim 18, arguments used in rejection of claim 5 and 6 applies.
Regarding claim 19, arguments used in rejection of 6 applies.
Regarding claim 20, argument used in rejection of claim 2 applies.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MIN HUANG/ Primary Examiner, Art Unit 2827
Prosecution Insights