Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claims 1-20 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Rubin et al (US 2005/0240999, herein Rubin) in view of Ichiriu et al (US 2008/0071757, herein Ichiriu).
Regarding claim 1, Rubin teaches an apparatus, comprising:
a pattern match engine (Fig 2, [0149], pattern matching engine), comprising:
first detection logic configured to detect a first match of a first portion of a pattern to be matched ([0149-0150], detect pattern of input from parse tree matching pattern of interest).
Rubin fails to teach the apparatus comprising second detection logic configured to detect a second match of a second portion of the pattern to be matched.
Ichiriu teaches an apparatus comprising a pattern match engine comprising first and second detection logic configured to detect a first and second match of a first and second portion of a pattern to be matched (Abstract, Claims 1, 14, 16, [0073], [0142], NFA engine, [0132], [0144], [0150-151], NFA engines pattern match portions of input data).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Rubin and Ichiriu to utilize pattern matching against multiple portions of data. While Rubin does not explicitly state that the pattern matching engine may include multiple sections of logic for pattern-matching different portions of the patterns of interest, Ichiriu describes how pattern matching may be augmented by searching in parallel using multiple engines to detect patterns in parallel (Ichiriu [0113], [0115], parallel matching). As parallel processing is a routine and conventional paradigm in the processor art, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 2, the combination of Rubin and Ichiriu teaches the apparatus of claim 1, wherein the first detection logic is configured to generate a first high output when the first match of the first portion of the pattern to be matched is detected (Rubin [0149], return Boolean flag when pattern is matched).
Regarding claim 3, the combination of Rubin and Ichiriu teaches the apparatus of claim 2, wherein the second detection logic is configured to generate a second high output when the second match of the second portion of the pattern to be matched is detected (Rubin [0149], return Boolean flag when pattern is matched & Ichiriu [0161], claim 14, matching second portions of input to pattern).
Regarding claim 4, the combination of Rubin and Ichiriu teaches the apparatus of claim 3, wherein the pattern match engine comprises at least one Boolean element configured to receive the first high output a first indication of detection of the first match (Rubin [0149], return Boolean flag when pattern is matched).
Regarding claim 5, the combination of Rubin and Ichiriu teaches the apparatus of claim 4, wherein the at least one Boolean element is configured to receive the second high output as a second indication of detection of the second match (Rubin [0149], return Boolean flag when pattern is matched & Ichiriu [0161], claim 14, matching second portions of input to pattern).
Regarding claim 6, the combination of Rubin and Ichiriu teaches the apparatus of claim 5, wherein the at least one Boolean element is configured to perform at least one Boolean operation based upon the first indication and the second indication (Rubin [0149-0151], Boolean flag & additional actions to perform after a match is detected & Ichiriu [0161], claim 14, matching second portions of input to pattern).
Regarding claim 7, the combination of Rubin and Ichiriu teaches the apparatus of claim 1, wherein the pattern match engine comprises an input selection circuit configured to transmit an input upon which detection of the first match is determined (Ichiriu [0146], [0170], select engine and input string to process).
Regarding claim 8, the combination of Rubin and Ichiriu teaches the apparatus of claim 7, wherein the input selection circuit is configured to transmit a second input upon which detection of the second match is determined (Ichiriu [0146], selecting inputs, [0161], claim 14, matching second portions of input to pattern).
Regarding claim 9, the combination of Rubin and Ichiriu teaches the apparatus of claim 8, wherein the pattern match engine is configured to generate an output indicative of an entirety of a match of the pattern to be matched (Rubin [0151], return output indicating match & Ichiriu [0159-0162], output indications of pattern that was matched).
Claims 10-18 refer to a method embodiment of the apparatus embodiment of claims 1-9. Therefore, the above rejections for claims 1-9 are applicable to claims 10-18, respectively.
Claims 19-20 refer to a device embodiment of the apparatus embodiment of claims 1-2. Therefore, the above rejections for claims 1-2 are applicable to claims 19-20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Barton (US 7,913,239) discloses a processor for performing pattern matching on portions of input data.
Mangione-Smith (US 2008/0189784) discloses a processor for performing pattern matching on segments of a pattern.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183