Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1, 7 and 14
b. Pending: 1-20
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Information Disclosure Statement
The information disclosure statement (IDS) is submitted on 1/17/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Independent claims 1, 7 and 14 are generally narrative and indefinite, failing to conform with current U.S. practice. They appear to be a literal translation into English from a foreign document and are replete with grammatical and idiomatic errors.
Claim 1 recites: “a plurality of sections, each of the two first memory cell mats having a section of the plurality of sections, and each of the plurality of second memory cell mats having multiple sections of the plurality of sections”. This particular limitation is ambiguous.
Claim 7 recites: “a plurality of sections, wherein the edge memory cell matrix includes a section of the plurality of sections and the non-edge memory cell matrix includes two or more sections of the plurality of sections”. This particular limitation is ambiguous.
Claim 14 recites: “a plurality of sections, wherein each memory cell matrix of the plurality of memory cell matrices includes at least one section of the plurality of sections”. This particular limitation is ambiguous.
All the dependent claims 2-6, 8-13 and 15-20 carry the same deficit due to dependency and henceforth rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-8 and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Noguchi (US 20120320699).
Regarding independent claim 1, Noguchi discloses an apparatus (Figs. 1-2) comprising:
a memory bank (Fig. 1 shows memory cell array 101) including two first memory cell mats and a plurality of second memory cell mats arranged in line between the two first memory cell mats (Fig. 2 and [0065] describes that memory cell array 101 is constituted from a plurality of memory cell mats (also referred to as "memory mats") 1012);
a plurality of sections, each of the two first memory cell mats having a section of the plurality of sections, and each of the plurality of second memory cell mats having multiple sections of the plurality of sections (Fig. 2 shows partial array of memory mats. There could be any number of mats placed vertically and a number of sections can be drawn by bounding lines); and
a section selection control circuit configured to select at least one section of the plurality of sections based on a logic combination of a first set of row decode signals and a second set of row decode signals (Fig. 2 and [0067] describes that row decoder 102 includes an FX driver (FX_drv: first row decoding unit) 1021 that supplies a driving signal FX (composed of outputs FXT_0.about.FXT_3) to the sub word drivers (SWDs) and main word drivers (MWDs: second row decoding units) 1022),
wherein a number of memory cells in each of the multiple sections of the plurality of second memory cell mats is nearly equal to a number of memory cells in each of the two first memory cell mats (sections can be drawn by including any number of memory cells fulfilling the requirement).
Regarding claim 2, Noguchi disclose all the elements of claim 1 as above and further the first set of row decode signals comprises a first number of bits and the second set of row decode signals comprises a second number of bits, wherein the second number is different from the first number (Fig. 2 and [0067]-[0068] describes that row decoder 102 includes an FX driver (FX_drv: first row decoding unit) 1021 that supplies a driving signal FX (composed of outputs FXT_0.about.FXT_3) to the sub word drivers (SWDs) and main word drivers (MWDs: second row decoding units) 1022FX signal is composed of four bits and four word lines SWLs are assigned to one main word line MWL. It may also be as a matter of course configured that two, eight, or sixteen SWLs are assigned to one main word line MWL).
Regarding claim 3, Noguchi disclose all the elements of claim 1 as above and further each of the first set of row decode signals and the second set of row decode signals is based on common row address signals (Fig. 1 shows output from address input circuit 104 goes to row decoder 102 via other circuits).
Regarding claim 4, Noguchi disclose all the elements of claim 3 as above and further a section predecoder configured to decode a portion of the common row address signals (Fig. 1 and [0050] describes circuit 105 latches the address signal externally supplied to the address terminals ADD, and supplies a row address signal to a row decoder (X decoder) 102) and further configured to activate a section signal among a plurality of corresponding section signals responsive to the portion of common row address signals ([0051] describes that row decoder (X decoder) 102 decodes the row address signal to select a word line, and drives the word line selected by a word driver).
Regarding claim 5, Noguchi disclose all the elements of claim 1 as above and further the two first memory cell mats are edge memory cell mats, each edge memory cell mat located at an end of the memory bank (Fig. 2 shows a partial 2X2 mat array. When extended vertically at-least by another two mats, then top one and bottom ones are the edge mats).
Independent device claim 7 recites the same limitations of independent device claim 1 but drafted slightly different way. As for example: mats are written as matrices; first as edge and second as non-edge based on the positions of matrix. Henceforth claim 7 is rejected the same way as claim 1 above.
Claim 8 recites same limitations of claim 5 and henceforth rejected the same way as above.
Regarding claim 10, Noguchi disclose all the elements of claim 8 as above and further a sense amplifier between the edge memory cell matrix and the non-edge memory cell matrix adjacent to the edge memory cell matrix (Fig. 2 and [0066] describes sense amplifiers (SAMP) 1014) ,
wherein:
the non-edge memory cell matrix is adjacent the edge memory cell matrix; and the edge memory cell matrix comprises folded bit lines that extend from the sense amplifier to the end of the memory bank and further extend from the end towards the sense amplifier (FIG. 2 illustrates an open bit line system, as a bit line structure. The embodiments, however, are not limited to such a configuration, and a folded line system may be of course employed).
Claims 11 and 12 recite same limitations as above and henceforth rejected the same way.
Claims 6, 9 and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Noguchi (US 20120320699) in view of Choi et al. (US 20240057324).
Regarding claim 6, Noguchi disclose all the elements of claim 1 as above and through Choi further a number of word lines coupled to each of the plurality of second memory cell mats is equal to or greater than twice a number of word lines coupled to each of the two first memory cell mats (Figs. 2A-2B and [0047]-[0048] describes one set of banks with height h1 and another set with height h2).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Choi to modified Noguchi in order to provide with semiconductor memory device, in which a capacity of a bank may be expanded adaptively to a size of a package while operating condition(s) required for the semiconductor memory device are satisfied as taught by Choi ([0005]).
Claim 9 recites same limitations of claim 6 and henceforth rejected the same way as above.
Independent device claim 14 recites the same limitations of independent device claim 7 and claim 9 together but drafted slightly different way. Henceforth claim 14 is rejected the same way as claim 7 and claim 9 above by references Noguchi (US 20120320699) and Choi et al. (US 20240057324).
Claim 15 limitations are obvious matter of design choice of how sections and sub sections are defined.
Claim 16 depends on claim 14 and recites limitations of claim 8 and henceforth rejected by references Noguchi (US 20120320699) and Choi et al. (US 20240057324).
Claim 17 depends on claim 16 and recites limitations of claim 10 and henceforth rejected by references Noguchi (US 20120320699) and Choi et al. (US 20240057324).
Claim 18 limitations are obvious matter of design choice of how sections of second memory cell matrix and first memory cell matrix are defined.
Regarding claim 19, Noguchi and Choi together disclose all the elements of claim 18 as above and through Choi further the size of each section of the plurality of sections corresponds to a number of word lines coupled to each section (Figs. 2A-2B show that height h1 and 2*h1 corresponds to number of word lines).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Choi to modified Noguchi in order to provide with semiconductor memory device, in which a capacity of a bank may be expanded adaptively to a size of a package while operating condition(s) required for the semiconductor memory device are satisfied as taught by Choi ([0005]).
Regarding claim 20, Noguchi and Choi together disclose all the elements of claim 14 as above and through Noguchi further a bank (Fig. 2 shows bank 101) comprising a plurality of blocks (Fig. 2 shows multiple blocks 1012), the plurality of blocks comprising the plurality of memory cell matrices (1012 can be divided into multiple sections of memory cell matrices); and
a block decoder configured to decode a first portion of the row address signals and a second portion of the row address signals, and further configured to provide one or more block signals that are configured to activate one of the plurality of blocks responsive to the first portion of row address signals (Fig. 2 and [0067] describes that row decoder 102 includes an FX driver (FX_drv: first row decoding unit) 1021 that supplies a driving signal FX (composed of outputs FXT_0.about.FXT_3) to the sub word drivers (SWDs) and main word drivers (MWDs: second row decoding units) 1022).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SULTANA BEGUM whose telephone number is (571)431-0691. The examiner can normally be reached M-F 8 am - 5 pm.
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 9/11/2026
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