DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
In light of the amendment filed 3/5/26, the objection to the drawings is withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-10, and 12-21 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 2023/0124542) in view of Liao et al. (US 2025/0037660) and Zhai (US 2024/0363057).
Regarding claim 1, Hwang discloses a pixel circuit comprising: a first driving transistor comprising a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node (fig. 3, T1, ¶ 100-102; see also figs. 7-11);
a writing transistor configured to apply a data voltage to the second node in response to a compensation gate signal (fig. 3, T2, ¶ 101; see also figs. 7-11);
a first initialization transistor configured to apply an initialization voltage to the first node in response to a first initialization gate signal (fig. 3, T4, ¶ 104-105; see also figs. 7-11);
a second initialization transistor configured to apply the initialization voltage to the third node in response to a second initialization gate signal (fig. 3, T8, ¶ 110-111; see also figs. 7-11);
a second driving transistor comprising a control electrode connected to a fourth node, a first electrode receiving a first power voltage, and a second electrode connected to a fifth node and configured to apply a driving current (fig. 3, T9, ¶ 115-117; see also figs. 7-11);
a third initialization transistor configured to apply the initialization voltage to the fourth node (fig. 3, T12, ¶ 119-120; see also figs. 7-11);
a first capacitor configured to apply a sweep signal to the first node (fig. 3, C1, ¶ 112; see also figs. 7-11);
a second capacitor comprising a first electrode connected to the third node and a second electrode connected to the fourth node (fig. 3, C2, ¶ 124; see also figs. 7-11);
and a light emitting element configured to emit light based on the driving current (fig. 3, ED, ¶ 97-98; see also figs. 7-11).
Hwang fails to explicitly disclose the second initialization transistor being directly connected to the first driving transistor, and a third initialization gate signal.
Liao teaches the second initialization transistor being directly connected to the first driving transistor (fig. 1, fig. 6, ¶ 43, ¶ 56, M12 directly connected to M1).
Hwang and Liao are both directed to OLED pixel circuits with sweep signals. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Hwang with the device of Liao since such a modification simplifies the structure of the pixel circuit (Liao, ¶ 5).
Zhai teaches a third initialization gate signal (fig. 3, ¶ 62-64, ¶ 67, ¶ 92, M8 turned on via PAM_S1).
Hwang in view of Liao and Zhai are both directed to pixel circuits with PWM and PAM circuits. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Hwang in view of Liao with the device of Zhai since such a modification prevents fluctuations from affecting the gate reset of the driving transistor (Zhai, ¶ 92) and improves a freedom of regulating the flowing period of the driving current (Zhai, ¶ 81).
Regarding claim 3, Hwang discloses a first emission control transistor configured to apply the first power voltage to the second node in response to a first emission signal (fig. 3, T5, ¶ 106; see also figs. 7-11);
and a second emission control transistor configured to apply the driving current to the light emitting element in response to a second emission signal (fig. 3, T14, ¶ 122; see also figs. 7-11).
Regarding claim 4, Hwang discloses a first compensation transistor configured to connect the first node and the third node in response to the compensation gate signal (fig. 3, T3, ¶ 102-103; see also figs. 7-11);
and a second compensation transistor configured to connect the fourth node and the fifth node in response to a second compensation gate signal (fig. 3, T11, ¶ 117-118; see also figs. 7-11).
Regarding claim 5, Hwang discloses a fourth initialization transistor configured to apply a second power voltage different from the first power voltage to a first electrode of the light emitting element in response to the second initialization gate signal (fig. 3, T15, ¶ 123; see also figs. 7-11).
Regarding claim 6, Hwang discloses wherein a writing frame period, in which the pixel circuit is driven, comprises an applying period and a first emission period (fig. 3, fig. 7, ¶ 140-145, address period and plural emission periods),
and wherein in the applying period, the data voltage is applied to the first node and the initialization voltage is applied to the fourth node (fig. 3, figs. 7-10, ¶ 141-142, ¶ 152-160).
Regarding claim 7, Hwang discloses wherein in a first sub-emission period of the first emission period, the first emission signal has an inactivation level, the second emission signal has an inactivation level, the second initialization gate signal has an activation level, and the sweep signal has a first voltage level (fig. 3, figs. 7-10, ¶ 141-145, e.g., EP2 at t6, ¶ 150-160).
Regarding claim 8, Hwang discloses wherein in a second sub-emission period following the first sub-emission period of the first emission period, the first emission signal has an activation level, the second emission signal has an inactivation level (fig. 3, figs. 7-11, ¶ 141-145, e.g., EP2 at t7-t8, ¶ 150-160; see also ¶ 162-178).
Zhai further teaches the sweep signal has a second voltage level higher than the first voltage level (fig. 4, ¶ 81).
Regarding claim 9, Hwang discloses wherein in a third sub-emission period following the second sub-emission period of the first emission period, the first emission signal has an activation level, the second emission signal has an activation level, and the sweep signal is decreased from the second voltage level to a third voltage level lower than the first voltage level (fig. 3, figs. 7-11, ¶ 141-145, e.g., EP2 at t8, ¶ 150-160; see also ¶ 162-178).
Regarding claim 10, Hwang discloses wherein the writing frame period further comprises a second emission period following the first emission period, wherein in the first emission period, the light emitting element emits light, and wherein in the second emission period, the light emitting element emits light (fig. 3, fig. 7, ¶ 140-145, plural emission periods).
Regarding claim 12, Hwang discloses a first compensation transistor configured to connect the first node and the third node in response to the compensation gate signal (fig. 3, T3, ¶ 102-103; see also figs. 7-11);
and a second compensation transistor configured to connect the fourth node and a fifth node in response to a second compensation gate signal (fig. 3, T11, ¶ 117-118; see also figs. 7-11),
wherein a writing frame period in which the pixel circuit is driven comprises an initialization period, a compensation period, an applying period, and a first emission period (fig. 3, figs. 7-11, ¶ 141-145, e.g., t1-t8, ¶ 150-160; see also ¶ 162-178),
and wherein in the initialization period, the first initialization gate signal has an activation level, the third initialization gate signal has an activation level, and the second compensation gate signal has an inactivation level (fig. 7, fig. 9, e.g., t2, ¶ 141-145).
Zhai further teaches the second initialization gate signal has an inactivation level (figs. 38-41, ¶ 177-183, e.g., K3).
Regarding claim 13, Hwang discloses wherein in the compensation period following the initialization period, the third initialization gate signal has an inactivation level, and the second compensation gate signal has an activation level (fig. 7, fig. 10, e.g., t3, ¶ 141-145).
Regarding claim 14, Hwang discloses wherein in the applying period following the compensation period, the data voltage is applied to the first node (fig. 7, fig. 11, e.g., t4, ¶ 162-178).
Regarding claim 15, this claim is rejected under the same rationale as claim 7.
Regarding claim 16, this claim is rejected under the same rationale as claim 8.
Regarding claim 17, this claim is rejected under the same rationale as claim 9.
Regarding claim 18, this claim is rejected under the same rationale as claim 10.
Regarding claim 19, Hwang discloses a display apparatus comprising: a display panel comprising a pixel circuit (figs. 1-3, ¶ 64-80);
a gate driver configured to apply a gate signal to the display panel (fig. 1, ¶ 64-80, e.g., gate driver 110);
a data driver configured to apply a data voltage to the display panel (fig. 1, ¶ 64-80, data driver 200);
an emission driver configured to apply an emission signal to the display panel (fig. 1, ¶ 64-80, emission circuit 114);
and a driving controller configured to control the gate driver, the data driver and the emission driver (fig. 1, ¶ 64-80, timing controller 300).
The remaining limitations of claim 19 are rejected under the same rationale as claim 1.
Regarding claim 20, this claim is rejected under the same rationale as claims 6 and 10.
Regarding claim 21, Hwang discloses an electronic apparatus comprising: a display panel comprising a pixel circuit (figs. 1-3, ¶ 64-80);
a gate driver configured to apply a gate signal to the display panel (fig. 1, ¶ 64-80, e.g., gate driver 110);
a data driver configured to apply a data voltage to the display panel (fig. 1, ¶ 64-80, data driver 200);
an emission driver configured to apply an emission signal to the display panel (fig. 1, ¶ 64-80, emission circuit 114);
a driving controller configured to control the gate driver, the data driver, and the emission driver based on an input control signal (fig. 1, ¶ 64-80, timing controller 300);
and a processor configured to output the input control signal (fig. 1, ¶ 64-80, timing controller 300 receives digital video data; see also ¶ 62).
The remaining limitations of claim 21 are rejected under the same rationale as claim 1.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Hwang in view of Liao and Zhai as applied to claim 1 above, and further in view of Koo et al. (US 2004/0207583).
Regarding claim 2, Hwang in view of Liao and Zhai fails to disclose wherein a width-to-length (W/L) ratio of the second driving transistor is different based on a color of the light emitting element.
Koo teaches wherein a width-to-length (W/L) ratio of the second driving transistor is different based on a color of the light emitting element (abstract, ¶ 38-45, width or length of driving transistors different for different colors).
Hwang in view of Liao and Zhai and Koo are both directed to display devices with driving transistors. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Hwang in view of Liao and Zhai with the device of Koo since such a modification improves white balance (Koo, ¶ 45).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Hwang in view of Liao and Zhai as applied to claim 3 above, and further in view of Park et al. (US 2021/0125559).
Regarding claim 11, Hwang discloses wherein a frame period in which the pixel circuit is driven comprises: a writing frame in which the data voltage is applied and the light emitting element emits light (fig. 3, fig. 7, ¶ 140-145, address period and plural emission periods).
Hwang in view of Liao and Zhai fails to disclose a holding frame in which the data voltage is not applied and the light emitting element emits light.
Park teaches a holding frame in which the data voltage is not applied and the light emitting element emits light (abstract, fig. 4, ¶ 101-107, holding frames disclosed).
Hwang in view of Liao and Zhai and Park are both directed to OLED display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Hwang in view of Liao and Zhai with the device of Park since such a modification reduces power consumption (Park, ¶ 2) and provides a low frequency driving mode (Park, ¶ 102).
Response to Arguments
Applicant’s arguments with respect to claims 1, 19, and 21 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KEITH L CRAWLEY/Primary Examiner, Art Unit 2626
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