Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated Tamura (US 20160042681 A1).
Regarding claim 1:
Tamura US 20160042681 A1 discloses a display device (see Fig. 4) comprising:
a first pixel (110) in a first row and a first column ([0048-0058]); and
a second pixel (110) in a second row next to the first row and in the first column, wherein each of the first and second pixels comprises:
a light-emitting element (130) on a substrate (display substrate) (see Fig. 4[0072-
0074]);
a first transistor (121) configured to supply a driving current to a second node (node at 124) which is connected (electrically connected) to a first electrode of the light- emitting element (130) (see [0072-0073]), based on a voltage (vel) of a first node (node at 132)) which is connected to a gate electrode of the first transistor (121)(140 see Fig. 4) ([0072-0074;
a second transistor (122) connected to the first node (see Fig. 4, 0072-0074]); and wherein the third node (node at 122) of the first pixel (110) and the third node of the second pixel (110) are directly connected with each other (see Fig. 4, [0048-0058]).
a third transistor (122 for second pixel) connected between a third node (node at 122) which is connected to a drain electrode of the second transistor and the second node (node at 124), and
wherein the third node of the first pixel and the third node of the second pixel are directly connected with each other.
a third transistor (123) connected between a third node (node at 122) which is connected to a drain electrode of the second transistor (122) and the second node (node at 124) ([0072], Fig. 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim(s) 2-4, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tamura US 20160042681 A1 in view of Chung (US 20160125801 A1).
Regarding claim 2:
Tamura discloses an initialization voltage line (Vel) configured to supply an initialization voltage (see Tamura, Fig. 4, [0072]); and
a data line (14) configured to supply a data voltage (see Fig. 4), wherein each of the first and second pixels comprises:
a first capacitor (132) connected between first node (node at 132) and the initialization voltage line (Vel).
Tamura does not specifically disclose a second capacitor connected between the third node and the data line.
Chung discloses a second capacitor (c11) connected between the third node (N11) and the data line (Dj) (see Fig. 9, [0072-0073]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tamura with the teaching of Chung, thereby providing uniform brightness in the display device.
Regarding claim 3:
Note that Tamura discloses the first pixel and the second pixel are integrally formed (integrally form by third transistor and third node).
Chung US 20160125801 A1 discloses electrode of the second capacitor (c11,
see Fig. 9) of first pixel circuit intergraded (integrated through the third transistor and third node) with the adjacent pixels.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tamura with the teaching of , Chung, and thereby providing an high efficient data transmission in the display device.
Regarding claim 4:
Tamura in view of Chung discloses wherein the drain electrode of the second transistor (122) of the first pixel and the drain electrode of the second transistor of the second pixel are formed integrally (see the illustration of Fig. 4, [0072-0075]). Same motivation as applied to claim 2.
Regarding claim 11:
Tamura US 20160042681 A1 discloses a display device (see Fig. 4) comprising:
a first pixel (110) in a first row and a first column ([0048-0058]); and
a second pixel (110) in a second row next to the first row and in the first column, wherein each of the first and second pixels comprises:
a light-emitting element (130) on a substrate (display substrate) (see Fig. 4[0072-
0074]);
an initialization voltage line (Vin) configured to supply an initialization voltage (see Tamura, Fig. 4, [0072]); and a data line (14) configured to supply a data voltage (see Fig. 4),
a first transistor (121) configured to supply a driving current to a second node (node at 124) which is connected (electrically connected) to a first electrode of the light- emitting element (130) (see [0072-0073]), based on a voltage (vel) of a first node (node at 132)) which is connected to a gate electrode)(140 see Fig. 4) ([0072-0074]);
a first capacitor (132) connected between first node and the initialization voltage line (Vel); and
a second transistor (122) connected to the first node (see Fig. 4, 0072-0074]);
a third transistor (122) connected between a third node (node at 122) which is connected to a drain electrode of the second transistor and the second node (node at 124), and wherein the third node of the first pixel and the third node of the second pixel are directly connected with each other.
a third transistor (123) connected between a third node (node at 122) which is connected to a drain electrode of the second transistor (122) and the second node (node at 124) ([0072], Fig. 4).
a third transistor (122) electrically connecting the third node with the second node (124) ([0072], Fig. 4) and
Tamura does not specifically discloses a second capacitor connected between the third node and the data line; wherein a first electrode of the second capacitor of the first pixel and a first electrode of the second capacitor of the second pixel are formed integrally.
Chung discloses a second capacitor (c11) connected between the third node (N11) and the data line (Dj) (see Fig. 9, [0072-0073]), wherein a first electrode of the second capacitor (c11) of the first pixel and a first electrode of the second capacitor of the second pixel are formed integrally (integrated through the third transistor and third node with the adjacent pixels, see Fig. 9).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tamura with the teaching of , Chung, thereby providing uniform brightness in the display device.
5. Claim(s) 5-6, 8-9, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tamura US 20160042681 A1 in view of Chung (US 20160125801 A1) and further in view of NA (US 20150356920 A1).
Regarding claim 5:
Tamura in view of Chung discloses wherein each of the first and second pixels (in Fig. 4) comprises:
A substrate, comprises semiconductor region of each of the third transistor (122) and and first capacitor Chung discloses a first capacitor and a second capacitor (see Tamura Fig. 4 and Chung Fig. 9).
Tamura in view of Chung does not specifically disclose an active layer on the substrate and comprising a semiconductor region of each of the first to third transistors; a first capacitor,a first gate layer on the active layer and comprising a first electrode of the first capacitor; a second gate layer on the first gate layer and comprising a second electrode of the first capacitor; a first source metal layer on the second gate layer and comprising a capacitor electrode which is connected to the first electrode of the second capacitor; and
a second source metal layer on the first source metal layer and comprising the data line which is connected to the second electrode of the second capacitor.
NA (US 20150356920 A1) an active layer (162a) on the substrate (160,Fig. 13) and comprising a semiconductor region () of each of the first to third transistors (T1-T3); a first capacitor (cst), a first gate layer (164a) on the active layer and comprising a first electrode of the first capacitor (162a, see Fig. 12-13) ([0093-0098], [0107-0110]);
a second gate layer (164b) on the first gate layer and comprising a second electrode of the first capacitor ([0094-0098]);
a first source metal layer (166a) on the second gate layer and comprising a
capacitor electrode which is connected to the first electrode of the second capacitor (see Fig. 12-13) ([0093-0098], [0107-0110]); and a second source metal layer (166b) on the first source metal layer and comprising the data line (166c) which is connected to the second electrode of the second capacitor (CDT) (see [0093-0098], see Fig. 12-13) ([0093-0098], [0107-0110]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tamura with the teaching of Chung and Na, and thereby providing an accurate data transmission in the display device.
Regarding claim 6:
Tamura discloses wherein a capacitor electrode of the first pixel and the capacitor electrode of the second pixel are integrally formed (see Fig. 4, [0072-0073]).
Regarding claim 8:
Tamura discloses a third pixel (third 110) in the first row and a second column next to the first column (see the illustration of Fig. 1, [0067]); and
a fourth pixel (fourth 110) in the second row and in the second column, wherein each of the third and fourth pixels comprises: a light-emitting (130) element on a substrate (display substrate) ([0072-0073], Fig. 4);
a first transistor (121) configured to supply a driving current to a second node (node at 124) which is connected to a first electrode of the light-emitting element [see Fig. 4], based on a voltage of a first node (node at 132) which is connected to a gate electrode [0072-0073];
a second transistor (123) connected to the first node; and a third transistor (122) connected between a third node (node at 122) which is connected to a drain electrode of the second transistor and the second node (see Fig. 4, [0072-0073]), and wherein the third node of the third pixel and the third node of the fourth pixel are directly connected with each other (see Fig. 4, [0072-0073])
Regarding claim 9:
Tamura discloses wherein a source electrode of the first transistor (122) of the first pixel (110) and a source electrode of the first transistor of the third pixel (third 110 in first scan line) are formed integrally (see Fig.4, [0072-0073]).
Regarding claim 12:
Tamura discloses a first scan write line (scan line 12 for first pixel) configured to supply a first scan write signal to the second transistor of the first pixel ([0061-0065]);
a second scan write line (scan line 12 for second pixel) configured to supply a second scan write signal to the second transistor of the second pixel ([0061-0065], ); and
a scan control line (GELi) configured to supply a scan control signal to the third transistor of the first pixel and the third transistor of the second pixel (0064-0065).
Allowable subject matter
6. Claim 7, 10 and 13-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 7:
The closest art of record singly or in combination fails to teach or suggest the limitations “a first portion of the initialization voltage line (Vil) is in the second gate layer and extends in a first direction, and a second portion of the initialization voltage line is in a third source metal layer on the second source metal layer and extends in a second direction intersecting the first direction” (see Applicant’s disclosure [0098-0100], Fig. 8-9).
Regarding claim 10:
The closest art of record singly or in combination fails to teach or suggest the limitations “a first gate layer on the active layer; a second gate layer on the first gate layer; a first source metal layer on the second gate layer; a second source metal layer on the first source metal layer; and a third source metal layer comprising a driving voltage line on the second source metal layer, and wherein a source electrode of the first transistor of the first pixel and a source electrode of the first transistor of the third pixel share a single driving voltage line” (see Applicant’s disclosure [0098-0100], Fig. 8-9).
Regarding claim 13:
The closest art of record singly or in combination fails to teach a “a first source metal layer on the second gate layer and comprising a capacitor electrode which is connected to the first electrode of the second capacitor; anda second source metal layer on the first source metal layer and comprising the data line which is connected to the second electrode of the second capacitor (see Applicant’s disclosure [0098-0100], Fig. 8-9).
Responds to Applicant’s argument
7. Applicant’s argument filed on 02/05/2026 has been considered but are not persuasive. More specifically the Applicant argues that Exeminer’s cited reference Tamura (US 20160042681 A1) fails to disclose the limitations as recited in claim 1. Applicant also argues that Tamura in view of Chung (US 20160125801 A1) fails to teach the limitations as recited in claim 11.
In responds the Examiner disagrees with the Applicant’s point of view. Note that examiner’s cited reference explicitly discloses the subject matter as recited in the claim 1. Examine gives a broadest reasonable interpretation towards the claim limitations as recited in the claim. The limitations of the claim 11 are broad and combining the reference of Tamura and Chung in obvious to meet the limitations as recited in the claim 11.
Conclusion
8. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Inquiry
9. Any inquiry concerning this communication or earlier communication from the examiner should be directed to Shaheda Abdin whose telephone number is (571) 270-1673.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LunYi Lao could be reached at (571) 272-7671. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAHEDA A ABDIN/ Primary Examiner, Art Unit 2627
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