Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the response to this Office action, the Office respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Office in prosecuting this application.
The Office has cited particular figures, elements, paragraphs and/or columns and line numbers in the references as applied to the claims for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider each of the cited references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage disclosed by the Office.
Status of Claims
- Applicant’s Response filed February 13, 2026 is acknowledged.
- Claim(s) 3, 6, 7, 11-16, 21-24, 28-29 is/are withdrawn as non-elected
- Claim(s) 1-30 is/are pending in the application.
- Claim(s) 1-2, 4-5, 8-10, 17-20, 25-27, 30 is/are examined on the merits
Election/Restrictions
Applicant’s election without traverse of FIGS. 1-10 as Species A for pixel circuit and FIGS. 32-33 as Species B for display panel (claims 1-2, 4-5, 8-10, 17-20, 25-27 and 30) in the reply filed on February 13, 2026 is acknowledged.
Claims 3, 6, 7, 11-16, 21-24, 28-29 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on February 13, 2026.
Applicant is reminded that upon the cancelation of claims to a non-elected invention, the inventorship must be corrected in compliance with 37 CFR 1.48(a) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. A request to correct inventorship under 37 CFR 1.48(a) must be accompanied by an application data sheet in accordance with 37 CFR 1.76 that identifies each inventor by his or her legal name and by the processing fee required under 37 CFR 1.17(i).
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on January 17, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4, 19, 27 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tanada, U.S. Patent Publication No. 20010048106.
Consider claim 1, Tanada teaches a display panel (see Tanada figure 5) comprising: a data line (see Tanada figure 6B, element 610 source signal line);
a first pixel configured to store a first data voltage of the data line in a first capacitor in a first period of a data writing period (see Tanada figure 6B, element pixel A, and paragraph 0100 where pixel A has a first switching TFT 601, a first EL driver TFT 603, a first EL element 605 and a first storage capacitor 607. Paragraph 0223 where storage capacitor has a function of storing the voltage applied to the gate electrode of the EL driver TFT and paragraph 0102 where a signal is written only in the pixel A during this half period (705)); and
a second pixel configured to store a second data voltage of the data line in a second capacitor in a second period of the data writing period (see Tanada figure 6B, element pixel B, and paragraph 0100 where pixel B has a second switching TFT 602, a second EL driver TFT 604, a second EL element 606 and a second storage capacitor 608. Paragraph 0223 where storage capacitor has a function of storing the voltage applied to the gate electrode of the EL driver TFT and paragraph 0102 where a signal is written only in the pixel B during this half period (706)),
wherein the first pixel includes: a first-first transistor located in a first path from the data line to the first capacitor, and configured to be turned on in response to a first signal during the first period of the data writing period (see Tanada figure 6B, element 615 and paragraphs 0100-0102 where a signal is written only in the pixel A during this half period (705)), and
wherein the second pixel includes: a first-second transistor located in a second path from the data line to the second capacitor, and configured to be turned on in response to a second signal during the second period of the data writing period (see Tanada figure 6B, element 616 and paragraphs 0100-0102 where a signal is written only in the pixel B during this half period (706)).
Consider claim 2, Tanada teaches all the limitations of claim 1 and further teaches wherein the first signal and the second signal are a same signal having a first level in the first period of the data writing period and having a second level in the second period of the data writing period, and wherein the first-first transistor and the first-second transistor have different types from each other (see Tanada paragraph 0100 where A pixel selecting portion 613 in Embodiment 1 is composed of an n-channel TFT 615, a p-channel TFT 616 and a pixel selecting signal line 614. A Hi signal is inputted to the pixel selecting signal line to turn the n-channel TFT 615 conductive, so that a signal from the source signal line 610 is written in the pixel A. If a LO signal is inputted to the pixel selecting signal line, the p-channel TFT 616 is turned conductive so that a signal from the source signal line 610 is written in the pixel B).
Consider claim 4, Tanada teaches all the limitations of claim 1 and further teaches wherein the first pixel further includes: a second-first transistor connected in series with the first-first transistor in the first path, and configured to be turned on in response to a third signal during the data writing period (see Tanada figure 6B, element 601, 609 and paragraphs 0100-0102 where FIG. 7B shows the electric potential of a gate signal line 609 and of the pixel selecting signal line 614 in one of the sub-frame periods of FIG. 7A and gate signal line on the first row is selected (701)), and
wherein the second pixel further includes: a second-second transistor connected in series with the first-second transistor in the second path, and configured to be turned on in response to the third signal during the data writing period (see Tanada figure 6B, element 602, 609 and paragraphs 0100-0102 where FIG. 7B shows the electric potential of a gate signal line 609 and of the pixel selecting signal line 614 in one of the sub-frame periods of FIG. 7A and gate signal line on the first row is selected (701)).
Consider claim 19, Tanada teaches all the limitations of claim 1 and further teaches wherein a first light emitting element included in the first pixel and a second light emitting element included in the second pixel are light emitting elements of a same color (see Tanada paragraph 0118 where electronic device for monochrome gray scale display does not require to consider the difference in voltage-luminance characteristic between EL elements of different colors unlike an electronic device for color display).
Consider claim 27, Tanada teaches an electronic device comprising: a display panel (see Tanada figure 5); and
a power supply configured to provide power to the display panel (see Tanada paragraph 0098 where A power supply for supplying a current to EL elements is connected to current supply lines of the pixel portion 501),
wherein the display panel comprises: a first data line (see Tanada figure 6A, element 635);
a second data line (see Tanada figure 6A, element 645);
a first pixel configured to store a first data voltage of the first data line in a first capacitor in a first period of a data writing period (see Tanada figure 6B, element pixel A, and paragraph 0100 where pixel A has a first switching TFT 601, a first EL driver TFT 603, a first EL element 605 and a first storage capacitor 607. Paragraph 0223 where storage capacitor has a function of storing the voltage applied to the gate electrode of the EL driver TFT and paragraph 0102 where a signal is written only in the pixel A during this half period (705)); and
a second pixel configured to store a second data voltage of the second data line in a second capacitor in a second period of the data writing period (see Tanada figure 6B, element pixel B, and paragraph 0100 where pixel B has a second switching TFT 602, a second EL driver TFT 604, a second EL element 606 and a second storage capacitor 608. Paragraph 0223 where storage capacitor has a function of storing the voltage applied to the gate electrode of the EL driver TFT and paragraph 0102 where a signal is written only in the pixel B during this half period (706)),
wherein the first pixel includes: a first-first transistor located in a first path from the first data line to the first capacitor, and configured to be turned on in response to a first signal during the first period of the data writing period (see Tanada figure 6B, element 615 and paragraphs 0100-0102 where a signal is written only in the pixel A during this half period (705) where for example pixel A corresponds to the R pixel connected to 635 of the first row in figure 6A), and
wherein the second pixel includes: a first-second transistor located in a second path from the second data line to the second capacitor, and configured to be turned on in response to a second signal during the second period of the data writing period (see Tanada figure 6B, element 616 and paragraphs 0100-0102 where a signal is written only in the pixel B during this half period (706) where for example pixel B corresponds to the R pixel connected to 645 of the first row in figure 6A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5, 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanada, U.S. Patent Publication No. 20010048106 in view of ordinary skill.
Consider claim 5, Tanada teaches all the limitations of claim 4, and further teaches wherein the first signal and the second signal are a same signal (see Tanada paragraph 0100 where A pixel selecting portion 613 in Embodiment 1 is composed of an n-channel TFT 615, a p-channel TFT 616 and a pixel selecting signal line 614. A Hi signal is inputted to the pixel selecting signal line to turn the n-channel TFT 615 conductive, so that a signal from the source signal line 610 is written in the pixel A. If a LO signal is inputted to the pixel selecting signal line, the p-channel TFT 616 is turned conductive so that a signal from the source signal line 610 is written in the pixel B),
Tanada is silent regarding first and second signal are shifted by half of one horizontal time from the third signal.
As best understood by Examiner claim 5 appears to be directed towards figures 5-6 of Applicant’s disclosure:
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During period P1, each of T1-1b, T2-2b, T2-2b are ON, T1-2b while T1-2b is off; allowing a data signal to flow to the pixel PX1b.
During period P1, each of T1-2b, T2-2b, T2-2b are ON, T1-2b while T1-1b is off; allowing a data signal to flow to the pixel PX2b.
It is not readily apparent what benefit is derived by having the period prior to P1, transistor T1-1b is on in response to DEMUX[n]` and transistor T2-1b is off in response to GW[n]` (effectively blocking a signal DL from being provided to pixel PX1b) and during the period after P2, transistor T2-2b is off in response to GW[n]` and transistor T1-2b is on in response to DEMUX[n]` (effectively blocking a signal DL from being provided to pixel PX2b).
Particularly in view of the teaching of Tanda teaching which provides a functionally equivalent circuit. Specifically, the period prior to P1 and after P2 are not periods where a signal is being provided to the Applicant’s circuit of figure 5. Therefore, the on/off state combination of these transistors controlling when a data line signal is being provided to each pixel does not impact the function of the circuit of Tanda figure 6B as long as at least one of the gate signal line or the pixel selecting signal line for each pixel has an off signal.
The difference between the prior art and the claimed invention is that Tanda teaches a signal that turns on each of the pixel selecting transistors during the respective period that a data signal for each pixel is to be provided but does not discuss the state of the pixel transistor pairs 601/615 and 602/616 outside of the period that a data is being provided. One of ordinary skill would have recognized that during the period prior to data signal being provided to pixel A and after a data signal being provided to pixel B at least one of the transistors controlling providing a data signal to each pixel must be off to ensure that a signal from source data line 610 is only provided during appropriate time. There were a finite number of identified and predictable potential solutions to the recognized need or problem which were:
1. Provide a signal that is on for pixel A 601 transistor and off for pixel A transistor 615 during period prior to data signal being provided to pixel A and during period after data signal being provided to pixel B
2. Provide a signal that is off for pixel A 601 transistor and on for pixel A transistor 615 during period prior to data signal being provided to pixel A and during period after data signal being provided to pixel B
3. Provide a signal that is on for pixel B 602 transistor and off for pixel B transistor 616 during period prior to data signal being provided to pixel A and during period after data signal being provided to pixel B
4. Provide a signal that is off for pixel B 602 transistor and on for pixel B transistor 616 during period prior to data signal being provided to pixel A and during period after data signal being provided to pixel B
One of ordinary skill in the art could have pursued these finite and known potential solutions with a reasonable expectation of success since both solutions provide equivalent functionality of providing a data signal during the periods that a data signal is to be provided and blocking a data signal prior to and after a data signal is to be provided.
Absent any criticality (i.e., unobvious and/or unexpected result(s)), determining appropriate signals to turn transistor elements on to achieve functionally equivalent outcome is generally achievable through routine optimization/experimentation, and since discovering the optimum or workable signals, where the general conditions of a claim are disclosed in the prior art, involves only routine skill in the art, In re Aller, 105 USPQ 233 (CCPA 1955). Moreover, in the absence of any criticality (i.e., unobvious and/or unexpected result(s)), the parameter set forth above would have been obvious to a person having ordinary skill as discussed above. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Consider claim 8, Tanada teaches all the limitations of claim 1 and further teaches wherein the first pixel includes: the first-first transistor including a gate which receives the first signal (see Tanada figure 6B, element 614 and paragraph 0100-0102), a first terminal, and a second terminal (see Tanada figure 6B, element 615);
a second-first transistor including a gate which receives a third signal (see Tanada figure 6B, element 601, 609 and paragraphs 0100-0102), a first terminal connected to the data line (see Tanda figure 6B, element 601 with is connected to element 610 thru element 615), and a second terminal connected to the first terminal of the first-first transistor (obvious variation to exchange order of transistors 601 and 615 between the data line and the pixel circuit. One of ordinary skill would readily recognize that these transistors are in series therefore in order for the data signal to be transmitted to the pixel circuit both would necessarily need to be on and in order to block the data signal from being transmitted to the circuit, at least one of the transistors would necessarily need to be off. Exchanging the order of connection between the data line and the pixel circuit would amount to rearrangement of parts without altering functionality of the circuit);
a third-first transistor including a gate connected to the second terminal of the first-first transistor (see Tanada figure 6B, element 603 which is connected to the second terminal of the first transistor thru element 601), a first terminal which receives a first power supply voltage, and a second terminal (see Tanada figure 6B, element 611 corresponding to element 630, 640, 650 of figure 6A which are disclosed at paragraph 0104 as current supply lines 630 and 660 have to have the electric potential in accordance with R, the current supply lines 640 and 670 have to have the electric potential in accordance with G, and the current supply lines 650 and 680 have to have the electric potential in accordance with B);
the first capacitor including a first electrode connected to the gate of the third-first transistor, and a second electrode connected to the first terminal of the third-first transistor (see Tanada figure 6B, element 607, 603 where second electrode of capacitor connects to first terminal which receives power supply); and
a first light emitting element including an anode connected to the second terminal of the third-first transistor (see Tanada figure 6B, element 605), and
a cathode which receives a second power supply voltage (see Tanada figure 12A-12B and paragraph 0124 where electric potential of the cathode wiring 1206 is lower than the electric potential of the current supply line 1201), and
wherein the second pixel includes: the first-second transistor including a gate which receives the second signal (see Tanada figure 6B, element 614 and paragraph 0100-0102), a first terminal, and a second terminal (see Tanada figure 6B, element 616);
the second-second transistor including a gate which receives the third signal (see Tanada figure 6B, element 602, 609 and paragraphs 0100-0102), a first terminal connected to the data line (see Tanda figure 6B, element 602 with is connected to element 610 thru element 616), and a second terminal connected to the first terminal of the first-second transistor (obvious variation to exchange order of transistors 602 and 616 between the data line and the pixel circuit. One of ordinary skill would readily recognize that these transistors are in series therefore in order for the data signal to be transmitted to the pixel circuit both would necessarily need to be on and in order to block the data signal from being transmitted to the circuit, at least one of the transistors would necessarily need to be off. Exchanging the order of connection between the data line and the pixel circuit would amount to rearrangement of parts without altering functionality of the circuit);
a third-second transistor including a gate connected to the second terminal of the first-second transistor (see Tanada figure 6B, element 604 which is connected to the second terminal of the first transistor thru element 602), a first terminal which receives the first power supply voltage, and a second terminal (see Tanada figure 6B, element 612 corresponding to element 630, 640, 650 of figure 6A which are disclosed at paragraph 0104 as current supply lines 630 and 660 have to have the electric potential in accordance with R, the current supply lines 640 and 670 have to have the electric potential in accordance with G, and the current supply lines 650 and 680 have to have the electric potential in accordance with B);
the second capacitor including a first electrode connected to the gate of the third-second transistor, and a second electrode connected to the first terminal of the third-second transistor (see Tanada figure 6B, element 608, 604 where second electrode of capacitor connects to first terminal which receives power supply); and
a second light emitting element including an anode connected to the second terminal of the third-second transistor (see Tanada figure 6B, element 606), and
a cathode which receives the second power supply voltage (see Tanada figure 12A-12B and paragraph 0124 where electric potential of the cathode wiring 1206 is lower than the electric potential of the current supply line 1201).
Consider claim 9, Tanda teaches all the limitations of claim 8 and further teaches wherein the first signal and the second signal are a same demultiplexing signal having a first level in the first period of the data writing period and having a second level in the second period of the data writing period (see Tanda paragraphs 0100-0102 where A pixel selecting portion 613 in Embodiment 1 is composed of an n-channel TFT 615, a p-channel TFT 616 and a pixel selecting signal line 614. A Hi signal is inputted to the pixel selecting signal line to turn the n-channel TFT 615 conductive, so that a signal from the source signal line 610 is written in the pixel A. If a LO signal is inputted to the pixel selecting signal line, the p-channel TFT 616 is turned conductive so that a signal from the source signal line 610 is written in the pixel B),
wherein the third signal is a writing signal having the first level in the data writing period (see Tanda figure 7B electric potential of gate signal line and paragraphs 0100-0102 where for example gate signal line on the first row is selected (701)),
wherein the first-first transistor, the second-first transistor, the second-second transistor, the third-first transistor and the third-second transistor are P-type transistors, and wherein the first-second transistor is an N-type transistor (see Tanada paragraphs 0017, 0080, 0100-0102 where switching TFT and driver TFT may be either n-channel or p-channel and paragraph 0047, 0100-0102 where each pixel selecting portion has an n-channel transistor and a p-channel transistor).
Consider claim 10, Tanda teaches all the limitations of claim 8, wherein the first signal and the second signal are a same demultiplexing signal having a second level in the first period of the data writing period and having a first level in the second period of the data writing period (see Tanda paragraphs 0100-0102 where A pixel selecting portion 613 in Embodiment 1 is composed of an n-channel TFT 615, a p-channel TFT 616 and a pixel selecting signal line 614. A Hi signal is inputted to the pixel selecting signal line to turn the n-channel TFT 615 conductive, so that a signal from the source signal line 610 is written in the pixel A. If a LO signal is inputted to the pixel selecting signal line, the p-channel TFT 616 is turned conductive so that a signal from the source signal line 610 is written in the pixel B),
wherein the third signal is a writing signal having the second level in the data writing period (see Tanda figure 7B electric potential of gate signal line and paragraphs 0100-0102 where for example gate signal line on the first row is selected (701)),
wherein the first-first transistor, the second-first transistor, the second-second transistor, the third-first transistor and the third-second transistor are N-type transistors, and wherein the first-second transistor is a P-type transistor (see Tanada paragraphs 0017, 0080, 0100-0102 where switching TFT and driver TFT may be either n-channel or p-channel and paragraph 0047, 0100-0102 where each pixel selecting portion has an n-channel transistor and a p-channel transistor).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanada, U.S. Patent Publication No. 20010048106 in view of Park et al, U.S. Patent Publication No. 20230038359 and Lee et al, U.S. Patent Publication No. 20200126478.
Consider claim 17, Tanda teaches all the limitations of claim 1 and further teaches wherein the first pixel includes: the first-first transistor including a gate which receives the first signal (see Tanada figure 6B, element 614 and paragraph 0100-0102), a first terminal connected to the data line, and a second terminal (see Tanada figure 6B, element 615, 610);
a second-first transistor including a gate which receives a third signal (see Tanada figure 6B, element 601, 609 and paragraphs 0100-0102), a first terminal connected to the second terminal of the first-first transistor, and a second terminal (see Tanada figure 6B, element 601, 615);
a third-first transistor including a first gate connected to the second terminal of the second-first transistor, a first terminal, a second terminal and
the first capacitor including a first electrode connected to the first gate of the third-first transistor, and a second electrode connected to the second terminal (see Tanada figure 6B, element 607) and
a first light emitting element including an anode (see Tanada figure 6B, element 605)
a cathode which receives a second power supply voltage (see Tanada figure 12A-12B and paragraph 0124 where electric potential of the cathode wiring 1206 is lower than the electric potential of the current supply line 1201), and
wherein the second pixel includes: the first-second transistor including a gate which receives the second signal (see Tanada figure 6B, element 614 and paragraph 0100-0102), a first terminal connected to the data line, and a second terminal (see Tanada figure 6B, element 616);
a second-second transistor including a gate which receives the third signal (see Tanada figure 6B, element 602, 609 and paragraphs 0100-0102), a first terminal connected to the second terminal of the first-second transistor, and a second terminal (see Tanda figure 6B, element 602 with is connected to element 610 thru element 616);
a third-second transistor including a first gate connected to the second terminal of the second-second transistor, a first terminal, a second terminal (see Tanada figure 6B, element 604)
the second capacitor including a first electrode connected to the first gate of the third-second transistor, and a second electrode (see Tanada figure 6B, element 608, 604)
a second light emitting element including an anode (see Tanada figure 6B, element 606)
a cathode which receives the second power supply voltage (see Tanada figure 12A-12B and paragraph 0124 where electric potential of the cathode wiring 1206 is lower than the electric potential of the current supply line 1201).
Tanada teaches a simple pixel circuit having two transistors (601, 603) and one capacitor (607).
In a related field of endeavor, Park teaches a pixel circuit having a second-first transistor including a gate which receives a third signal,
a third-first transistor including a first gate connected to the second terminal of the second-first transistor (see Park figure 3, element T2), a first terminal, a second terminal and a second gate (see Park figure 3, element T1 and paragraph 0095 where T1 may further include a bottom gate (not shown) so as to improve an operating characteristic of the first transistor T1);
the first capacitor including a first electrode connected to the first gate of the third-first transistor, and a second electrode connected to the second terminal and the second gate of the third-first transistor (see Park figure 3, Cst);
a third capacitor including a first electrode which receives a first power supply voltage, and a second electrode connected to the second terminal and the second gate of the third-first transistor (see Park figure 3, element Chold and paragraph 0095 where the bottom gate may be connected to a common node connecting the hold capacitor Chold and the first parasitic capacitor Cld of the light emitting element LD);
a fourth-first transistor including a gate which receives a fourth signal, a first terminal which receives a reference voltage, and a second terminal connected to the first gate of the third-first transistor (see Park figure 3, element T3, VREF, GRi, N1);
a fifth-first transistor including a gate which receives a fifth signal, a first terminal which receives the first power supply voltage, and a second terminal connected to the first terminal of the third-first transistor (see Park figure 3, element T5, VDD, EMi);
a seventh-first transistor including a gate which receives a seventh signal, a first terminal, and a second terminal which receives an initialization voltage (see Park figure 3, element T4, GIi, VINT, N2); and
a first light emitting element including an anode
Park is silent regarding a sixth-first transistor including a gate which receives a sixth signal, a first terminal connected to the second terminal and the second gate of the third-first transistor, and a second terminal.
In the same field of endeavor, Lee teach a sixth-first transistor including a gate which receives a sixth signal, a first terminal connected to the second terminal and the second gate of the third-first transistor, and a second terminal so as to control current provided to the light emitting element (see Lee figure 8, element T5). One of ordinary skill would have been motivated to modify the pixel circuit of Park to have a sixth transistor so as to control current provided to the light emitting element. Further, one of ordinary skill would have been motivated to have modified Tanada with the pixel circuit of Park/Lee so as to improve display by incorporating an initialization operation and threshold compensation.
Incorporation of the pixel circuit of Park/Lee with Tanada would result in having the recited features of claim 17.
Claim(s) 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanada, U.S. Patent Publication No. 20010048106 in view of Park et al, U.S. Patent Publication No. 20230038359.
Consider claim 30, Tanada teaches a display device comprising: a display panel (see Tanada figure 5) including a data line (see Tanada figure 6B, element 610 source signal line),
a first pixel configured to store a first data voltage of the data line in a first capacitor in a first period of a data writing period (see Tanada figure 6B, element pixel A, and paragraph 0100 where pixel A has a first switching TFT 601, a first EL driver TFT 603, a first EL element 605 and a first storage capacitor 607. Paragraph 0223 where storage capacitor has a function of storing the voltage applied to the gate electrode of the EL driver TFT and paragraph 0102 where a signal is written only in the pixel A during this half period (705)), and
a second pixel configured to store a second data voltage of the data line in a second capacitor in a second period of the data writing period (see Tanada figure 6B, element pixel B, and paragraph 0100 where pixel B has a second switching TFT 602, a second EL driver TFT 604, a second EL element 606 and a second storage capacitor 608. Paragraph 0223 where storage capacitor has a function of storing the voltage applied to the gate electrode of the EL driver TFT and paragraph 0102 where a signal is written only in the pixel B during this half period (706));
a scan driver configured to provide a first signal, a second signal and a writing signal having an on-level during the data writing period to the first pixel and the second pixel (see Tanada figure 5, element 506, 507 and paragraphs 0100-0102 where gate signal line corresponds to a writing signal, HI signal corresponds to a first signal and LO signal corresponds to a second signal);
a data driver configured to provide the first data voltage and the second data voltage to the first pixel and the second pixel through the data line (see Tanada figure 5, element 502 source signal line driver); and
wherein the first pixel includes: a first-first transistor located in a first path from the data line to the first capacitor, and configured to be turned on in response to the first signal during the first period of the data writing period (see Tanada figure 6B, element 615 and paragraphs 0100-0102 where a signal is written only in the pixel A during this half period (705)), and
wherein the second pixel includes: a first-second transistor located in a second path from the data line to the second capacitor, and configured to be turned on in response to the second signal during the second period of the data writing period (see Tanada figure 6B, element 616 and paragraphs 0100-0102 where a signal is written only in the pixel B during this half period (706)).
Tanada is silent regarding a controller configured to control the scan driver and the data driver. In the same field of endeavor, Park teaches a timing controller so as to generate control signals for data driver and scan driver control (see Park figure 1, element 600 and paragraph 0075).
One of ordinary skill would have been motivated to have modified Tanada to have a timing controller so as to generate control signals for data driver and scan driver control using known techniques with predictable results.
Allowable Subject Matter
Claim(s) 18, 20 25-26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The claimed invention recites
Claim 18 “The display panel of claim 17, wherein the third signal is a writing signal, the fourth signal is a reference signal, the fifth signal is a first emission signal, the sixth signal is a second emission signal, the seventh signal is an initialization signal, and the first signal and the second signal are the initialization signal, and wherein the first-first transistor and the first-second transistor have different types from each other. ”
Claim 20 “The display panel of claim 1, wherein the first pixel includes: a first pixel circuit including the first capacitor and the first-first transistor, and configured to generate a first driving current based on the first data voltage; and a first light emitting element connected to the first pixel circuit, and configured to emit light based on the first driving current, and wherein the second pixel includes: a second pixel circuit including the second capacitor and the first-second transistor, and configured to generate a second driving current based on the second data voltage; and a second light emitting element including an anode extension, connected to the second pixel circuit through the anode extension, and configured to emit light based on the second driving current.”
Claim 25 “The display panel of claim 1, wherein the first pixel includes a first pixel circuit located in a first row and a first column, and a first red light emitting element located in the first row and the first column, wherein the second pixel includes a second pixel circuit located in the first row and a second column, and a second red light emitting element located in a second row and the second and third columns, and wherein the display panel further comprises: a third pixel including a third pixel circuit located in the first row and the third column, and a first blue light emitting element located in the first row and the second and third columns; a fourth pixel including a fourth pixel circuit located in the first row and a fourth column, and a second blue light emitting element located in the second row and the fourth and fifth columns; a fifth pixel including a fifth pixel circuit located in the second row and the first column, and a first green light emitting element located in the second row and the first and second columns; a sixth pixel including a sixth pixel circuit located in the second row and the second column, and a second green light emitting element located in a third row and the first and second columns; a seventh pixel including a seventh pixel circuit located in the second row and the third column, and a third green light emitting element located in the second row and the third and fourth columns; and an eighth pixel circuit located in the second row and the fourth column, and a fourth green light emitting element located in the third row and the third and fourth columns. ”
The following prior arts are representative of the state of the prior art:
Tanada et al, U.S. Patent Publication No. 20010048106 (figures 6A-7B
Ueno, U.S. Patent Publication No. 20230186848 (figures 1-4)
Park et al, U.S. Patent Publication No. 20230038359 ( figure 3)
Seo et al, U.S. Patent Publication No. 20230290313 (figure 4A-4B)
The prior arts cited fails to fairly teach or suggest the combined features of the invention including the recited features of dependent claims 18, 20 and 25. Claim 26 is allowable by virtue of being dependent upon a claim reciting allowable subject matter.
These features find support at least at figures 7, 32 of Applicant’s original specification.
As such, modification of the prior art of record can only be motivated by hindsight reasoning, or by changing the intended use and function of the prior art themselves. Therefore, it is not clear that one of ordinary skill in the art would have made the necessary modifications to the prior art of record to encompass the limitations set forth in the present application. Moreover, none of the prior arts of record, taken either alone or in combination, anticipate nor render obvious the claimed inventions. Hence, claims 18, 20, 25-26 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee et al, U.S. Patent Publication No. 7656368 (display device), Yang et al, U.S. Patent Publication No. 20110221715 (display device), Ota, U.S. Patent Publication No. 20110221789 (display device), Kwon et al, U.S. Patent Publication No. 20150243720 (display device), Kwon et al, U.S. Patent Publication No. 9276050(display device), Jeon et al, U.S. Patent Publication No. 20160104409 (display device), Gong et al, U.S. Patent Publication No. 20180144685 (display device), Hwang et al, U.S. Patent Publication No. 20190279563 (display panel), Shang et al, U.S. Patent Publication No. 20230200155 (display device), Bae et al, U.S. Patent Publication No. 20240112630 (display device).
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/Dorothy Harris/Primary Examiner, Art Unit 2625