DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Continuity
Examiner notes this application is a child in a line of applications from parent application 13/685,186.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/1/25 has been considered by the examiner.
Drawings
The original drawings received on 1/17/25 are approved.
Claim Objections
Claims 1-7, 10, 13-15 and 17-20 are objected to because of the following informalities:
In claim 1, last two lines “a node between adjacent switches within the plurality of switches” has already been recited on lines 9-10 and should use a different nomenclature.
In claim 5, last two lines “a node between adjacent switches within the plurality of switches” has already been recited in claim 1 and should use a different nomenclature.
In claim 6, lines 3-4, “a node between adjacent switches within the plurality of switches” has already been recited in independent claim 1 and should use a different nomenclature.
In claim 6, last two lines “a node between adjacent switches within the plurality of switches” has already been recited and should use a different nomenclature.
In claim 10, lines 2-3, “a node between adjacent switches within the plurality of switches” has already been recited in independent claim 8 and should use a different nomenclature.
In claim 13, “a node between adjacent switches within the plurality of switches” has been recited earlier in the claim and should use a different nomenclature.
In claim 13, line 18, “a reference potential” has already been recited earlier in the claim and should have antecedent basis.
In claim 17, line 1, “the first terminal” lacks antecedent basis.
In claim 18, “a node between adjacent switches within the plurality of switches” has already been recited earlier in the claim and should use a different nomenclature.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.
Claim(s) 1-5, 8-10 and 16-17 are rejected under pre-AIA 35 U.S.C. 102b as being anticipated by Oraw (US 2009/0322384).
With respect to claim 1, Oraw discloses a charge pump circuit (Fig. 1C 221) comprising: an input terminal (Fig. 1C terminal Vin) configured to receive a first voltage (Fig. 1C Vin); an output terminal (Fig. 1C terminal Vo) configured to provide a second voltage (Fig. 1C Vo); a switching network (Fig. 1C 221) configured to be coupled to the input and output terminals, the switching network configured to operate in a first state of operation (Fig. 1C A) and a second state of operation (Fig. 1C B), the switching network including: a plurality of switches (Fig. 1C S1-S6) coupled between the input terminal and the output terminal; a first plurality of capacitors (Fig. 1C C5-C7) each having a first terminal and a second terminal, each of the first plurality of capacitors having its first terminal coupled to a node (Fig. 1C nodes S1-S2,S3-S4,S5-S6) between adjacent switches within the plurality of switches; a first phase pump (Fig. 1C S7-S8) coupled between the output terminal and a reference potential (Fig. 1C ground), the first phase pump being configured to be synchronized (Fig. 1C A,B) with a transition of the switching network between the first state of operation and the second state of operation; and
wherein the first plurality of capacitors includes at least a first capacitor (Fig. 1C C7) having its second terminal (Fig. 1C terminal to S7-S8) coupled to the first phase pump, and wherein the first plurality of capacitors includes at least a second capacitor (Fig. 1C C6) having its second terminal coupled to a node (Fig. 1C node S5-S6) between adjacent switches within the plurality of switches.
With respect to claim 2, Oraw discloses the charge pump circuit of claim 1 wherein the first terminal (Fig. 1C terminal S5-S6) of the first capacitor (Fig. 1C C7) and the second terminal (Fig. 1C terminal S5-S6) of the second capacitor (Fig. 1C C6) are coupled to a common node (Fig. 1C node S5-S6) between adjacent switches within the plurality of switches.
With respect to claim 3, Oraw discloses the charge pump circuit of claim 1 wherein the first voltage (Fig. 1C Vin) received at the input terminal is a multiple (Fig. 1C Vin = 4*Vo) of the second voltage (Fig. 1C Vo) provided at the output terminal.
With respect to claim 4, Oraw discloses the charge pump circuit of claim 1 wherein the first plurality of capacitors includes at least a third capacitor (Fig. 1C C5) having its second terminal (Fig. 1C terminal S3-S4) coupled (Fig. 1C coupled through S4-S5) to the first phase pump.
With respect to claim 5, Oraw discloses the charge pump circuit of claim 1 wherein the first plurality of capacitors includes at least a third capacitor (Fig.1C C5) having its second terminal coupled to a node (Fig. 1C node S3-S4) between adjacent switches within the plurality of switches.
With respect to claim 8, Oraw discloses a charge pump circuit comprising: an input terminal configured to receive a first voltage (Fig. 1C Vin); an output terminal configured to provide a second voltage (Fig. 1C Vo); a switching network (Fig. 1C 221) configured to be coupled to the input and output terminals, the switching network configured to operate in a first state of operation (Fig. 1C A) and a second state of
operation (Fig. 1C B), the switching network including: a plurality of switches (Fig. 1C S1-S6) coupled in series between the input terminal and the output terminal; a plurality of capacitors (Fig. 1C C5-C7) each having a first terminal and a second terminal, each of the plurality of capacitors having its first terminal coupled to a node (Fig. 1C nodes S1-S2,S3-S4,S5-S6) between adjacent switches within the plurality of switches; a phase pump (Fig. 1C S7-S8) coupled between the output terminal and a reference potential (Fig. 1C ground), the phase pump being configured to be synchronized (Fig. 1C A,B) with a transition of the switching network between the first state of operation and the second state of operation; wherein the plurality of capacitors includes: a first capacitor (Fig. 1C C7) having its first terminal coupled to a first node (Fig. 1C node S5-S6) within the plurality of switches and its second terminal (Fig. 1C terminal at S7-S*) coupled to the phase pump; and a second capacitor (Fig. 1C C6) having its first terminal coupled to a second node (Fig. 1C node S3-S4) within the plurality of switches and its second terminal (Fig. 1C terminal at S5-S6) coupled (Fig. 1C C6 terminal coupled through S6) to the phase pump, the second node (Fig. 1C node S3-S4) being separated from the first node (Fig. 1C node S5-S6) by no more than two switches (Fig. 1C nodes separated by S4 and S5).
With respect to claim 9, Oraw discloses the charge pump of claim 8 wherein the first voltage received at the input terminal is a multiple (Fig. 1C Vin = 4 * Vo) of the second voltage provided at the output terminal.
With respect to claim 10, Oraw discloses the charge pump circuit of claim 8 wherein the plurality of capacitors includes a third capacitor (Fig. 1C C5) having its first terminal coupled to a node (Fig. 1C node S1-S2) between adjacent switches within the plurality of switches, and having its second terminal (Fig. 1C terminal at S3-S4) coupled to one of the first (Fig. 1C coupled to node S5-S6 through S4 and S5) and second nodes (Fig. 1C coupled to node S3-S4) within the plurality of switches.
With respect to claim 16, Oraw discloses a method of operating a charge pump, comprising: providing a switching network (Fig. 1C 221) coupled to an input terminal for receiving an input voltage (Fig. 1C Vin) and coupled to an output terminal for providing an output voltage (Fig. 1C Vo), wherein the switching network includes a plurality of switches (Fig. 1C S1-S6) interconnected with each other, and wherein two adjacent switches are joined to each other along an intermediate node (Fig. 1C node Sn to Sn+1); controlling the switching network to alternate between first (Fig. 1C A) and second (Fig. 1C B) states; providing a phase pump (Fig. 1C S7-S8) coupled between the output terminal and a reference potential (Fig. 1C ground), and configuring the phase pump to be synchronized (Fig. 1C A,B) with the first and second states of the switching network; coupling a first terminal (Fig. 1C terminal at S5-S6) of a first capacitor (Fig. 1C C7) to a first node (Fig. 1C node S5-S6) of the switching network and coupling a second terminal (Fig. 1C terminal at S7-S8) of the first capacitor to the phase pump; and coupling a first terminal (Fig. 1C terminal at S3-S4) of a second capacitor (Fig. 1C C6) to a second node (Fig. 1C S5-S6) of the switching network and coupling (Fig. 1C S6 coupled to phase pump through S6) a second terminal (Fig. 1C terminal at S5-S6) of the second capacitor to the phase pump, wherein the second node (Fig. 1C node S5-S6) is separated from the first node (Fig. 1C node S5-S6) by no more than two switches (Fig. 1C nodes coupled together).
With respect to claim 17, Oraw discloses the method of claim 16, including coupling the first terminal of a third capacitor (Fig. 1C C5) to the switching network and coupling the second terminal (Fig. 1C terminal at S3-S4) of the third capacitor to one of the first (Fig. 1C coupled through S4-S5) and second (Fig. 1C coupled through S4-S5) nodes.
Claim(s) 1, 6-7, 11, 13 and 18-20 are rejected under pre-AIA 35 U.S.C. 102b as being anticipated by Kamijo (US 2005/0007184).
With respect to claim 1, Kamijo discloses a charge pump circuit (Fig. 10 300) comprising: an input terminal (Fig. 10 terminal VLO-2) configured to receive a first voltage (Fig. 10 VLC-2); an output terminal (Fig. 10 terminal Vout) configured to provide a second voltage (Fig. 10 Vout); a switching network (Fig. 10 300) configured to be coupled to the input and output terminals, the switching network configured to operate in a first state of operation (Fig. 10 ON) and a second state of operation (Fig. 10 OFF), the switching network including: a plurality of switches (Fig. 10 HP1-HP5) coupled between the input terminal and the output terminal; a first plurality of capacitors (Fig. 10 C1,C3) each having a first terminal and a second terminal, each of the first plurality of capacitors having its first terminal coupled to a node (Fig. 10 nodes VLO-3,VLO-5) between adjacent switches within the plurality of switches; a first phase pump (Fig. 10 LP1,LN1) coupled between the output terminal and a reference potential (Fig. 10 VSS), the first phase pump being configured to be synchronized (Fig. 3 FIRST PERIOD,SECOND PERIOD of S1 synchronized with S3-S10) with a transition of the switching network between the first state of operation and the second state of operation; and
wherein the first plurality of capacitors includes at least a first capacitor (Fig. 10 C1) having its second terminal (Fig. 10 terminal to VLO-2) coupled to the first phase pump, and wherein the first plurality of capacitors includes at least a second capacitor (Fig. 10 C3) having its second terminal coupled (Fig. 10 coupled through LP1,HP1) to a node (Fig. 10 node at VLO-3) between adjacent switches (Fig. 10 HP1,HP2) within the plurality of switches.
With respect to claim 6, Kamijo discloses the charge pump circuit of claim 1 further comprising: a second plurality of capacitors (Fig. 10 C2,C4) each having a first terminal and a second terminal, each of the second plurality of capacitors having its first terminal (Fig. 10 node VLO-4,VLO-6) coupled to a node between adjacent switches within the plurality of switches; and a second phase pump (LP2,LN2) coupled between the output terminal and a reference potential, the second phase pump being configured to be synchronized (Fig. 3 FIRST PERIOD,SECOND PERIOD of S2 synchronized with S3-S10) with a transition of the switching network between the first state of operation and the second state of operation; and wherein the second plurality of capacitors includes at least a third capacitor (Fig. 10 C2) having its second terminal (Fig. 10 terminal at VLO-1) coupled to the second phase pump, and wherein the second plurality of capacitors includes at least a fourth capacitor (Fig. 10 C4) having its second terminal (Fig. 10 terminal at VLO-1) coupled (Fig. 10 coupled through LP2 and HP1) to a node (Fig. 10 LVO-3) between adjacent switches (Fig. 10 HP2,HP1) within the plurality of switches.
With respect to claim 7, Kamijo discloses the charge pump circuit of claim 6 wherein the first terminal (Fig. 10 termial VLO-4) of the third capacitor (Fig. 10 C2) and the second terminal (Fig. 4 terminal at VLO-1) of the fourth capacitor (Fig. 10 C4) are coupled (Fig. 10 coupled by HP2,HP1,LP2) to a common node (Fig. 10 node at VLO-4) between adjacent switches (Fig. 10 HP3,HP2) within the plurality of switches.
With respect to claim 11, Kamijo discloses a charge pump circuit comprising: an input terminal (Fig. 10 terminal at VLC-2) configured to receive a first voltage (Fig. 10 VLC-2); an output terminal (Fig. 10 terminal at Vout) configured to provide a second voltage (Fig. 10 Vout); a switching network (Fig. 10 300) configured to be coupled to the input and output terminals, the switching network configured to operate in a first state of operation (Fig. 10 ON) and a second state of operation (Fig. 10 OFF), the switching network including: a plurality of switches (Fig. 10 HP1-HPn+1, see paragraph 124 for multiplication by N) coupled between the input terminal and the output terminal; a first plurality of capacitors (as in Fig. 10 C1,C3,Cn for an arbitrary N as in paragraph 124) each having a first terminal and a second terminal, each of the first plurality of capacitors having its first terminal coupled to a node (Fig. 10 nodes VLO_3,VLO-5,VLO-N) between adjacent switches within the plurality of switches; and a second plurality of capacitors (Fig. 10 C2,C4) each having a first terminal and a second terminal, each of the second plurality of capacitors having its first terminal coupled to a node (Fig. 10 node VLO-4,VLO-6,VLO-N+1) between adjacent switches within the plurality of switches; a first phase pump (Fig. 10 LP1,LN1) coupled between the output terminal and a reference potential (Fig. 10 VSS), the first phase pump being configured to be synchronized (Fig. 3 S1 synchronized to FIRST PERIOD, SECOND PERIOD of S3-S10) with a transition of the switching network between its first state of operation and its second state of operation; a second phase pump (Fig. 10 LP2,LN2) coupled between the output terminal and a reference potential (Fig. 10 VSS), the second phase pump being configured to be synchronized (Fig. 3 S2 synchronized with S3-S10) with a transition of the switching network between its first state of operation and its second state of operation; wherein the first plurality of capacitors includes a first capacitor (Fig. 10 C1), a second capacitor (Fig. 10 C3), and a third capacitor (Fig. 10 illustrates N=5, but paragraph 124 discloses an arbitrary number, for N=7 would have additional capacitor Cn), the first capacitor having its second terminal (Fig. 10 terminal VLO-2) coupled (Fig. 10 coupled through HP3-HP1) to the first terminal (Fig. 10 terminal VLO-5) of the second capacitor, and the second terminals (Fig. 10 VLO-2) of the second (Fig. 10 C3) and third capacitors (Fig. 10 Cn) being coupled (Fig. 10 VLO-2) to the first phase pump; and wherein, the second plurality of capacitors includes a fourth capacitor (Fig. 10 C2), a fifth capacitor (Fig. 10 C4), and a sixth capacitor (Fig. 10 illustrates N=5, but paragraph 124 discloses an arbitrary number, for N=7 would have additional capacitor Cn+1), the fourth capacitor having its second terminal coupled (Fig. 10 VLO-1) to the first terminal (Fig. 10 VLO-6) of the fifth capacitor, and the second terminals (Fig. 10 VLO-1) of the fifth and sixth capacitors being coupled (Fig. 10 VLO-1) to the second phase pump.
With respect to claim 13, Kamijo discloses a charge pump circuit comprising: an input terminal configured to receive a first voltage (Fig. 10 VLC-2); an output terminal configured to provide a second voltage (Fig. 10 Vout); a switching network (Fig. 10 300) configured to be coupled to the input and output terminals, the switching network configured to operate in a first state of operation (Fig. 10 ON) and a second state of operation (Fig. 10 OFF), the switching network including: a plurality of switches (Fig. 10 HP1-HPn+1, see paragraph 124 for multiplication by N) coupled between the input terminal and the output terminal; a first plurality of capacitors (as in Fig. 10 C1,C3,Cn-2 for N=7) each having a first terminal and a second terminal, each of the first plurality of capacitors having its first terminal coupled to a node (Fig. 10 node VLO-3,VLO-5,VLO-N) between adjacent switches within the plurality of switches; and a second plurality of capacitors (Fig. 10 C2,C4,Cn-1) each having a first terminal and a second terminal, each of the second plurality of capacitors having its first terminal coupled to a node (Fig. 10 node VLO-4,VLO-6,VLOn+1) between adjacent switches within the plurality of switches; a first phase pump (Fig. 10 Lp1,Ln1) coupled between the output terminal and a reference potential (Fig. 10 ), the first phase pump being configured to be synchronized (Fig. 3 FIRST PERIOD,SECOND PERIOD of S1 synchronized with S3-S10) with a transition of the switching network between its first state of operation and its second state of operation; a second phase pump (Fig. 10 Lp2,Ln2) coupled between the output terminal and a reference potential (Fig. 10 VSS), the second phase pump being configured to be synchronized (Fig. 3 FIRST PERIOD,SECOND PERIOD of S2 synchronized with S3-S10) with a transition of the switching network between its first state of operation and its second state of operation; wherein the first plurality of capacitors includes a first capacitor (Fig. 10 C1), a second capacitor (Fig. 10 C3), and a third capacitor (Fig. 10 Cn-2), the first capacitor having its second terminal (Fig. 10 VLO-2) coupled (Fig. 10 coupled through LP1,HP1) to a node (Fig. 10 VLO-3) between adjacent switches (Fig. 10 HP2,HP1) within the plurality of switches, the second terminal (Fig. 10 VLO-2) of the second capacitor being coupled (Fig. 10 VLO-2) to the second terminal (Fig. 10 VLO-2) of the first capacitor, and the second terminal (Fig. 10 VLO-2) of the third capacitor being coupled to the first phase pump; and wherein the second plurality of capacitors includes a fourth capacitor (Fig. 10 C2), a fifth capacitor (Fig. 10 C4), and a sixth capacitor (Fig. 10 C6), the fourth capacitor having its second terminal coupled (Fig. 10 coupled through LP2,HP1) to a node (Fig. 10 VLO-3) between adjacent switches (Fig. 10 HP2,HP1) within the plurality of switches, the second terminal (Fig. 10 VLO-1) of the fifth capacitor being coupled to the second terminal (Fig. 10 VLO-1) of the fourth capacitor, and the second terminal (Fig. 10 VLO-1) of the sixth capacitor being coupled to the second phase pump.
With respect to claim 18, Kamijo discloses a method of operating a charge pump, comprising: providing a switching network (Fig. 10 300) coupled to an input terminal for receiving an input voltage (Fig. 10 VLC-2) and coupled to an output terminal for providing an output voltage (Fig. 10 Vout), wherein the switching network includes a plurality of switches (Fig. 10 HP1-HPn, see paragraph 124 for N=7) interconnected with each other, and wherein two adjacent switches are joined to each other along an intermediate node (Fig. 10 node HPn-HPn+1); controlling the switching network to alternate between first (Fig. 10 ON) and second states (Fig. 10 OFF); providing a first phase pump (Fig. 10 LP1,LN1) coupled between the output terminal and a reference potential (Fig. 10 VSS), and configuring the first phase pump to be synchronized (Fig. 3 S1 synchronized with S3-S10) with the first and second states of the switching network; providing a second phase pump (Fig. 10 LP2,LN2) coupled between the output terminal and the reference potential (Fig. 10 VSS), and configuring the second phase pump to be synchronized (Fig. S2 synchronized with S3-S10) with the first and second states of the switching network; providing first (Fig. 10 C1), second (Fig. 10 C3) and third capacitors (Fig. 10 Cn-2), coupling a first terminal of each of the first, second and third capacitors to a respective node (Fig. 10 node HPx-HPx+1) between adjacent switches within the switching network, coupling (Fig. 10 coupling through HP1,LP1) a second terminal (Fig. 10 terminal VLO-2) of the first capacitor to a node (Fig. 10 node VLO-3) between adjacent switches (Fig. 10 HP2,HP1) within the switching network and coupling the second terminal (Fig. 10 terminal at VLO-2) of the first capacitor (Fig. 10 C1) to a second terminal (Fig. 10 terminal at VLO-2) of the second capacitor (Fig. 10 C3), and coupling a second terminal (Fig. 10 terminal at VLO-2) of the third capacitor (Fig. 10 Cn-2 as in paragraph 124 for N=7) to the first phase pump; and providing fourth (Fig. 10 C2), fifth (Fig. 10 C4) and sixth capacitors (Fig. 10 Cn-1, as in paragraph 124 for N=7), coupling a first terminal (Fig. 10 terminal at HPx-HPx+1) of each of the fourth, fifth and sixth capacitors to a respective node (Fig. 10 node HPx-HPx+1) between adjacent switches within the switching network, coupling (Fig. 10 coupling through LP2 and HP1) a second terminal (Fig. 10 terminal at VLO-1) of the fourth capacitor to a node (Fig. 10 node VLO-1) between adjacent switches (Fig. 10 HP1-HP2) within the switching network and coupling the second terminal (Fig. 10 terminal at VLO-1) of the fourth capacitor (Fig. 10 C2) to a second terminal (Fig. 10 terminal at VLO-1) of the fifth capacitor (Fig. 10 C4), and coupling a second terminal (Fig. 10 terminal at VLO-1) of the sixth capacitor (Fig. 10 Cn-1 as in paragraph 124 with N=7) to the second phase pump.
With respect to claim 19, Kamijo discloses the method of claim 18, including:
during the first state of operation, coupling the first capacitor, the third capacitor, the
fifth capacitor, and the first phase pump, between the input terminal and the output terminal (Fig. 10 LP1 ON); and during the second state of operation, coupling the second capacitor, the fourth capacitor, the sixth capacitor, and the second phase pump, between the input terminal and the output terminal (Fig. 10 LP2 ON).
With respect to claim 20, Kamijo discloses the method of claim 19, including: during the first state of operation, coupling the sixth capacitor (Fig. 10 Cn-1) and the second phase pump between the output terminal and the reference potential (Fig. 10 LN2 ON); and during the second state of operation, coupling the third capacitor (Fig. 10 Cn-2) and the first phase pump between the output terminal and the reference potential (Fig. 10 LN1 ON).
Allowable Subject Matter
Claims 12 and 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if applicable claim objections as stated above were overcome. The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 12, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, wherein the switching network is configured wherein: during the first state of operation, the first capacitor is coupled in series with the second capacitor and with the first phase pump between the input terminal and the output terminal, and the sixth capacitor and the second phase pump are coupled in series between the output terminal and the reference potential; and during the second state of operation, the fourth capacitor is coupled in series with the fifth capacitor and with the second phase pump between the input terminal and the output terminal, and the third capacitor and the first phase pump are coupled in series between the output terminal and the reference potential.
With respect to claim 14, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, wherein the switching network is configured wherein: during the first state of operation, the first capacitor is coupled in series with the fifth capacitor, with the third capacitor, and with the first phase pump between the input terminal and the output terminal; and during the second state of operation, the fourth capacitor is coupled in series with the second capacitor, with the sixth capacitor and with the second phase pump between the input terminal and the output terminal.
The aforementioned limitations in combination with all remaining limitations of the respective claims are believed to render the aforementioned indicated claim and any dependent claims thereof patentable over the art of record.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY RAYMOND BEHM whose telephone number is (571)272-8929. The examiner can normally be reached M-F: 8-5 EST.
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/HARRY R BEHM/Primary Examiner, Art Unit 2838
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