Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated January 18, 2025, claims 1-20 are active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Foreign Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)
(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statements filed January 18, 2025 and August 14, 2025 have been
considered.
Claim Objections
Claims 3-9 and 12-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections- 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Frougier et al. [US Patent Application # 20230086181].
With respect to claim 1, Frougier et al. disclose a semiconductor device [figs. 5 and 6] comprising: a reference layer [RL of any top level (2-n) of fig. 5] having a fixed spin direction; a metal layer disposed below the reference layer [FL 1 of any respective top level of fig. 5 (refer to fig. 6)]; a first free layer [FL2 of any respective top level of fig. 5 (refer to fig. 6)] disposed below the metal layer; a first spin orbit coupling (SOC) layer [Bottom SHE Line of any respective top level of fig. 5 (refer to fig. 6)] disposed below the first free layer, and configured to control a spin direction recorded in the first free layer by using a current flowing through the first SOC layer [I wrte/2 (fig. 6)]; a second free layer [FL2 of any respective lower level of fig. 5 (for example, level 1 is the lower level of level 2)] disposed below the first SOC layer; and a second SOC layer [the respective lower level’s Bottom SHE line] disposed below the second free layer, and configured to control a spin direction recorded in the second free layer by using a current flowing through the second SOC layer [same as the first].
With respect to claim 2, Frougier et al. disclose a barrier layer disposed between the reference layer and the metal layer, between the metal layer and the first free layer, or between the first SOC layer and the second free layer. Fig. 6 shows an MgO layer between the reference layer and the metal layer.
Claim(s) 10 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Frougier et al. [US Patent Application # 20230086181].
With respect to claim 10, Frougier et al. disclose a semiconductor device [figs. 5 and 6] comprising: a reference layer [RL of any top level (2-n) of fig. 5] having a fixed spin direction; a first free layer [FL2 of any respective top level of fig. 5 (refer to fig. 6)] disposed below the reference layer; a first spin orbit coupling (SOC) layer [Bottom SHE Line of any respective top level of fig. 5 (refer to fig. 6)] disposed below the first free layer, and configured to control a spin direction recorded in the first free layer by using a current flowing through the first SOC layer [I wrte/2 (fig. 6)]; a second free layer [FL2 of any respective lower level of fig. 5 (for example, level 1 is the lower level of level 2)] disposed below the first SOC layer; and a second SOC layer [the respective lower level’s Bottom SHE line] disposed below the second free layer, and configured to control a spin direction recorded in the second free layer by using a current flowing through the second SOC layer [same as the first].
With respect to claim 11, Frougier et al. disclose a barrier layer disposed between the reference layer and the first free layer, or between the first SOC layer and the second free layer. Fig. 6 shows an MgO layer between the reference layer and the metal layer.
Allowable Subject Matter
Claims 18-20 are allowable over the prior art of record.
The following is an Examiner's statement of reasons for the indication of
allowable subject matter: the prior art of records does not show (in addition to the other
elements in the claim) the following:
-with respect to claim 3. The device of claim 1, further comprising: a first transistor controlled by a first word line signal to selectively connect the metal layer and a source line to each other; a second transistor controlled by a second word line signal to selectively connect the first SOC layer and the source line to each other; and a third transistor controlled by a third word line signal to selectively connect the second SOC layer and the source line to each other.
-with respect to claim 6. The device of The device of further comprising a readout transistor configured to selectively connect the reference layer and a readout bit line to each other, wherein the reference layer is connected to the readout bit line through the readout transistor, the first SOC layer is connected to the source line through the second transistor, and the spin direction of the first free layer is determined by measuring a resistance value of a first stacked structure including the reference layer, the metal layer, the first free layer, and the first SOC layer.
-with respect to claim 12: The device of claim 10, further comprising: a first transistor controlled by a first word line signal to selectively connect the first SOC layer and a source line to each other; and a second transistor controlled by a second word line signal to selectively connecting the second SOC layer and the source line to each other.
-with respect to claim 18, configured to control the spin direction of the first free layer by using a current flowing through the first SOC layer; a second free layer disposed below the first SOC layer, and having a physical property in which a resistance value of the second free layer is determined to a value corresponding to a second digit of the ternary number, based on a spin direction of the second free layer; and a second SOC layer disposed below the second free layer, and configured to control the spin direction of the second free layer by using a current flowing through the second SOC layer.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 June 27, 2026
Prosecution Insights