DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites the limitation "the second gate low voltage" in line 3 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipate by Lee et al. (US 2022/0208930 A1).
As to claim 11, Lee et al. teaches a display device ([0054]: display device) comprising: a driving voltage line (172 in Fig. 4;[0073]: driving voltage line 172) disposed on a substrate ([0073]: substrate 110); a first transistor (T1 in Fig. 4;[0086]: semiconductor layer 1130 of the driving transistor T1 includes a first region 1131, a channel 1132, and a second region 1133) disposed on the driving voltage line(172 in Fig. 4;[0073]: driving voltage line 172); a light emitting element (ED in Fig. 2;[0062]: light emitting diode ED) configured to receive a driving current flowing through the first transistor (T1 in Fig. 2;[0064]); a second transistor (T3 in Fig. 2) configured to initialize a first node to a first initialization voltage based on a first gate signal ([0066]: initialization transistor T3 turned on according to the first scan signal SC, thereby transmitting the initialization voltage INIT to the anode of the light emitting diode ED) , the first node being a first electrode of the light emitting element ([0066]: transmitting the initialization voltage INIT to the anode of the light emitting diode ED); and a gate low voltage line (173 in Fig. 4; [0073]: initialization voltage line 173) disposed at a same layer as the driving voltage line (172 in Fig. 4;[0073]: driving voltage line 172) and electrically connected to a bias electrode of the second transistor ([0104]: electrode 3175 of initialization transistor T3, Fig. 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 7-8 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2024/0282259 A1).
As to claim 1, Wu et al. teaches a display device (Abstract: display device) comprising: a light emitting element (30 in Fig. 3; [0053]: light emitting element 30 in Fig. 3) disposed on a substrate (BS in Fig. 3;[0053]: substrate BS) ; a first transistor (T1 in Fig. 7) configured to control a driving current flowing to a first node (N4 in Fig. 7) that is a first electrode of the light emitting element ([0053]: light emitting element;[0074]: driving transistor T1 outputs a driving current to drive the light-emitting element); a second transistor (T7 in Fig. 7) configured to initialize the first node (N4 in Fig. 7) to a first initialization voltage ([0071]: initialization signal) based on a first gate signal (SCAN signal in Fig. 7) having a first gate low voltage ([0068]: reset transistor T7 is connected with the first electrode E1 of the light-emitting element 100b, and is configured to reset the first electrode E1 of the light-emitting element;[0098]: transistors are all P-type;[0138]: transistor of P-type, the turn-on voltage is a low voltage (e.g., 0 V))). This embodiment does not disclose a gate low voltage line configured to supply a second gate low voltage lower than the first gate low voltage to a bias electrode of the second transistor.
However, in another embodiment, Wu teaches a gate low voltage line configured to supply a second gate low voltage ([0131]: first initialization signal Vinit1 is in a range of −3V to −2.5V, the second initialization signal Vinit2 is in a range of −2.5V to −2V ; note that the claim does not recite second gate low voltage is different from first initialization voltage) lower than the first gate low voltage ([0138]: transistor of P-type, the turn-on voltage is a low voltage (e.g., 0 V)) to a bias electrode of the second transistor ([0080-0082]: first electrode T71 of reset transistor T7. Second electrode T72 of the second reset transistor T7 is connected with the first electrode E1 of the light-emitting element 100b; [0098]: transistors are all P-type).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wu such that a gate low voltage line is configured to supply a second gate low voltage lower than the first gate low voltage to a bias electrode of the second transistor as taught by another embodiment of Wu et al. in order to improve uniformity of display image.
As to claim 2, Wu et al. teaches the display device of claim 1, further comprising: a third transistor (T2 in Fig. 7) configured to supply a data voltage to a second node (N2 in Fig. 7) based on a second gate signal ([0140]: transistor T2 receives the scan signal SCAN and the data signal DATA and writes the data signal DATA to the first electrode of the driving transistor T1 according to the scan signal SCAN), the second node (N2 in Fig. 7) being a first electrode of the first transistor (T1 in Fig. 7); a fourth transistor (T3 in Fig. 7) electrically connecting a third node (N3 in Fig. 7) and a fourth node (N1 in Fig. 7) to each other based on a third gate signal ([0069]: gate line GT supply scan signal;[0084]: gate electrode T30 of the threshold compensation transistor T3 is connected with the gate line GT), the third node(N3 in Fig. 7) being a second electrode of the first transistor (T1 in Fig. 7) and the fourth node (N1 in Fig. 7) being a gate electrode of the first transistor (T1 in Fig. 7); and a fifth transistor (T6 in Fig. 7) configured to initialize the fourth node (N1 in Fig. 7) to a second initialization voltage ([0072];[0078]: third initialization signal line INT3 is connected with the gate electrode of the driving transistor T1 through the first reset transistor T6; [0082]: first electrode T61 of the first reset transistor T6 is connected with the third initialization signal line INT3) based on a fourth gate signal (RESET1 in Fig. 7). As to claim 3, Wu et al. teaches the display device of claim 2, further comprising: a driving voltage line configured to supply a driving voltage ([0069]: power supply line PL1 is configured to supply a constant first voltage signal VDD); a sixth transistor (T4 in Fig. 7) electrically connecting the driving voltage line (PL1 in Fig. 7;[0069]: power supply line PL1) and the second node (N2 in Fig. 7) to each other based on an emission signal (EM in Fig. 7; [0069]: light-emitting control signal line EML is configured to supply a light-emitting control signal EM); and a seventh transistor (T5 in Fig. 7) electrically connecting the third node (N3 in Fig. 7) and the first node (N4 in Fig. 7) to each other based on the emission signal (EM in Fig. 7; [0069]: light-emitting control signal line EML is configured to supply a light-emitting control signal EM). As to claim 7, Wu et al. teaches the display device of claim 2, wherein the fourth transistor (T3 in Fig. 7) and the fifth transistor (T6 in Fig. 7) each include an oxide-based semiconductor region ([0098]: metal oxide semiconductor), and the second transistor (T7 in Fig. 7) includes a silicon-based semiconductor region ([0098]: monocrystalline silicon, polycrystalline silicon (such as low temperature polycrystalline silicon).
As to claim 8, Wu et al. teaches the display device of claim 2, wherein the second transistor (T7 in Fig. 5), the fourth transistor (T3 in Fig. 5), and the fifth transistor (T6 in Fig. 5) each include a silicon-based semiconductor region ([0098]: monocrystalline silicon, polycrystalline silicon (such as low temperature polycrystalline silicon), and the gate low voltage line is configured to supply the second gate low voltage to a bias electrode of the fifth transistor (Fig. 5 shows electrode T61 of transistor T6 is supplied with initialization signal Vinit1;[0131]: first initialization signal Vinit1 is in a range of −3V to −2.5V).
As to claim 21, Wu et al. teaches a display device (Abstract: display device) comprising: a light emitting element (30 in Fig. 3; [0053]: light emitting element 30 in Fig. 3) disposed on a substrate (BS in Fig. 3;[0053]: substrate BS) ;
a first transistor (T1 in Fig. 7) configured to control a driving current flowing to the light emitting element ([0053]: light emitting element;[0074]: driving transistor T1 outputs a driving current to drive the light-emitting element); a second transistor (T6 in Fig. 7) configured to initialize a gate electrode of the first transistor (T1 in Fig. 7) to a first initialization voltage based on a first gate signal having a first gate low voltage ([0076]:reset the gate electrode of the driving transistor T1;[0078]: initialization signal line INT3 is connected with the gate electrode of the driving transistor T1 through first reset transistor T6). This embodiment does not disclose a gate low voltage line configured to supply a second gate low voltage lower than the first gate low voltage to a bias electrode of the second transistor.
However, in another embodiment, Wu teaches a gate low voltage line configured to supply a second gate low voltage ([0131]: first initialization signal Vinit1 is in a range of −3V to −2.5V, note that the claim does not recite second gate low voltage is different from first initialization voltage) lower than the first gate low voltage ([0138]: transistor of P-type, the turn-on voltage is a low voltage (e.g., 0 V)) to a bias electrode of the second transistor ([0080];[0082]: first electrode T61 of reset transistor T6; [0098]: transistors are all P-type).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wu such that a gate low voltage line is configured to supply a second gate low voltage lower than the first gate low voltage to a bias electrode of the second transistor as taught by another embodiment of Wu et al. in order to improve uniformity of display image.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2024/0282259 A1) in view of Lee et al. (US 2022/0208930 A1).
As to claim 4, Wu teaches the display device of claim 3, but does not explicitly disclose wherein the driving voltage line and the gate low voltage line are disposed at a lower layer of a semiconductor region of the second transistor.
However, Lee et al. teaches wherein the driving voltage line (172 in Fig. 4; [0073]: driving voltage line 172) and the gate low voltage line (173 in Fig. 4; [0073]: initialization voltage line 173) are disposed at a lower layer of a semiconductor region of the second transistor ([0104]: electrode 3175 of initialization transistor T3, Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wu such that the driving voltage line and the gate low voltage line are disposed at a lower layer of a semiconductor region of the second transistor as taught by Lee et al. in order to prevent a short circuit of the signal lines caused by static electricity.
Claim(s) 6 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2024/0282259 A1) in view of Na et al. (US 2023/0206847A1)
As to claim 6, Wu et al. teaches the display device of claim 3, but does not explicitly disclose further comprising an eighth transistor configured to supply a bias voltage to the second node based on the first gate signal.
However, Na et al. teaches an eighth transistor (ST8 in Fig. 6) configured to supply a bias voltage to the second node based on the first gate signal ([0139]: bias voltage line VEHL supplied with a bias voltage;[0154]: eighth transistor ST8 may be turned on by the scan signal of the fourth scan line GB to electrically connect the bias voltage line VEHL to the first electrode of the first transistor ST1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wu et al. with an eighth transistor configured to supply a bias voltage to the second node based on the first gate signal as taught by Na et al. in order to minimize the potential fluctuation of high voltage line. As to claim 9, Wu et al. teaches the display device of claim 2, but does not explicitly disclose further comprising a plurality of stages configured to supply the first to fourth gate signals,wherein the gate low voltage line is configured to supply the second gate low voltage to the plurality of stages.
However, Na et al. teaches further comprising a plurality of stages configured to supply the first to fourth gate signals ([0096-0100];[0113]: stages), wherein the gate low voltage line is configured to supply the second gate low voltage to the plurality of stages ([0088]: first low-voltage line VGLL for applying a first low voltage VGL1, second low-voltage line VGLO for applying a second low voltage VGL2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wu et al. with a plurality of stages configured to supply the first to fourth gate signals, wherein the gate low voltage line is configured to supply the second gate low voltage to the plurality of stages as taught by Na et al. in order to apply voltage to the scan lines and display an image.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2024/0282259 A1) in view of Shin et al. (US 2020/0020263 A1).
As to claim 10, Wu et al. teaches the display device of claim 2, but does not explicitly disclose further comprising a plurality of stages configured to supply the first to fourth gate signals,wherein the gate low voltage line is insulated from the plurality of stages. However, Shin et al. teaches further comprising a plurality of stages configured to supply the first to fourth gate signals ([0010]: stages;[0052]: gate lines G1 to Gn for applying signals to the pixels PX;[0058]), wherein the gate low voltage line (G1 in Fig. 5;[0100]: gate line G1) is insulated (140 in Fig. 5; [0101]: insulating layer 140) from the plurality of stages (insulating layer 140 between stage connection line 178 and gate line G1 in Fig. 5;[0062]: stages; [0099];[0101]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wu et al. with a plurality of stages configured to supply the first to fourth gate signals, wherein the gate low voltage line is insulated from the plurality of stages as taught by Shin et al. in order to provide display device including a gate driver capable of facilitating
defect inspection of gate line.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2022/0208930 A1) in view of Wu et al. (US 2024/0282259 A1).
As to claim 12, Lee et al. teaches the display device of claim 11, but does not explicitly disclose wherein a low level of the first gate signal corresponds to a first gate low voltage, and the gate low voltage line is configured to supply a second gate low voltage lower than the first gate low voltage. However, Wu et al. teaches wherein a low level of the first gate signal corresponds to a first gate low voltage ([0138]: transistor of P-type, the turn-on voltage is a low voltage (e.g., 0 V)), and the gate low voltage line is configured to supply a second gate low voltage ([0131]: first initialization signal Vinit1 is in a range of −3V to −2.5V; note that the claim does not recite second gate low voltage is different from first initialization voltage) lower than the first gate low voltage ([0138]: transistor of P-type, the turn-on voltage is a low voltage (e.g., 0 V)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee et al. such that a low level of the first gate signal corresponds to a first gate low voltage, and the gate low voltage line is configured to supply a second gate low voltage lower than the first gate low voltage as taught by Wu et al. in order to reset the light emitting element.
Claim(s) 13-14 and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2022/0208930 A1) in view of Na et al. (US 2023/0206847 A1).
As to claim 13, Lee et al. teaches the display device of claim 11, further comprising:a third transistor (T2 in Fig. 2) configured to supply a data voltage to a second node based on a second gate signal ([0064-0065]: transistor T2 turned on according to the first scan signal SC, thereby transmitting a reference voltage or the data voltage DA to the gate electrode of the driving transistor T1) , the second node being a first electrode of the first transistor (T1 in Fig. 2); but does not explicitly disclose a fourth transistor electrically connecting a third node and a fourth node to each other based on a third gate signal, the third node being a second electrode of the first transistor and the fourth node being a gate electrode of the first transistor; and a fifth transistor configured to initialize the fourth node to a second initialization voltage based on a fourth gate signal. However, Na et al. teaches a fourth transistor (ST4 in Fig. 7) electrically connecting a third node and a fourth node to each other based on a third gate signal ([0149]: transistor ST4 disposed between the gate electrode of the first transistor ST1 and the second electrode of the first transistor ST1 turned on by the scan signal of the third scan line GC to electrically connect the gate electrode of the first transistor ST1 to the second electrode), the third node being a second electrode of the first transistor (ST1 in Fig. 6) and the fourth node being a gate electrode of the first transistor (ST1 in Fig. 6;[0149]); and a fifth transistor (ST3 in Fig. 6) configured to initialize the fourth node to a second initialization voltage based on a fourth gate signal ([0148]: third transistor ST3 turned on by the scan signal of the first scan line GI to electrically connect the gate electrode of the first transistor ST1 to the first initialization voltage line VIL1 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee et al. with a fourth transistor electrically connecting a third node and a fourth node to each other based on a third gate signal, the third node being a second electrode of the first transistor and the fourth node being a gate electrode of the first transistor, and a fifth transistor configured to initialize the fourth node to a second initialization voltage based on a fourth gate signal as taught by Na et al. in order to minimize the potential fluctuation of high voltage line. As to claim 14, Lee et al. teaches the display device of claim 13, but does not explicitly disclose further comprising: a sixth transistor electrically connecting the driving voltage line and the second node to each other based on an emission signal; a seventh transistor electrically connecting the third node and the first node to each other based on the emission signal; and an eighth transistor configured to supply a bias voltage to the second node based on the first gate signal. However, Na et al. teaches a third transistor (ST2 in Fig. 6) configured to supply a data voltage to a second node based on a second gate signal ([0147]:turned on by the scan signal of scan line GW to connect the first electrode of the first transistor ST1 to the data line DL) ;
a sixth transistor (ST5 in Fig. 6) electrically connecting the driving voltage line (VDDL in Fig. 9) and the second node to each other based on an emission signal ([0150]: transistor ST5 turned on by the emission signal of the emission line EM to electrically connect the first electrode of the first transistor ST1 to the first driving voltage line VDDL); and a seventh transistor (ST6 in Fig. 6) electrically connecting the third node and the first node to each other based on the emission signal (EM in Fig. 7; [0151]: transistor ST6 turned on by the emission signal of the emission line EM to electrically connect the second electrode of the first transistor ST1 to the anode electrode of the light emitting element EL); and
an eighth transistor (ST8 in Fig. 6) configured to supply a bias voltage to the second node based on the first gate signal ([0139]: bias voltage line VEHL supplied with a bias voltage; [0154]: eighth transistor ST8 may be turned on by the scan signal of the fourth scan line GB to electrically connect the bias voltage line VEHL to the first electrode of the first transistor ST1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee et al. with a third transistor configured to supply a data voltage to a second node based on a second gate signal, a sixth transistor electrically connecting the driving voltage line and the second node to each other based on an emission signal, a seventh transistor electrically connecting the third node and the first node to each other based on the emission signal, and an eighth transistor configured to supply a bias voltage to the second node based on the first gate signal.as taught by Na et al. in order to minimize the potential fluctuation of high voltage line.
As to claim 17, Lee et al. teaches the display device of claim 13, and the second transistor includes a silicon-based semiconductor region ([0084-0085]: silicon) but does not explicitly disclose wherein the fifth transistor includes an oxide-based semiconductor region. However, Na et al. teaches wherein the fifth transistor includes an oxide-based semiconductor region ([0157]: oxide semiconductor).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee et al. such that the fifth transistor includes an oxide-based semiconductor as taught by Na et al. in order to decrease leakage current and reduce power consumption.
As to claim 18, Lee et al. teaches the display device of claim 13, the second transistor each include a silicon-based semiconductor region ([0084-0085]: silicon), but does not explicitly disclose wherein the fifth transistor include a silicon-based semiconductor region, and the gate low voltage line is configured to supply the second gate low voltage to a bias electrode of the fifth transistor. However, Na et al. teaches wherein the fifth transistor include a silicon-based semiconductor region ([0157]: silicon), and the gate low voltage line is configured to supply the second gate low voltage to a bias electrode of the fifth transistor(ST3 in Fig. 6; [0148]: third transistor ST3 turned on by the scan signal of the first scan line GI to electrically connect the gate electrode of the first transistor ST1 to the first initialization voltage line VIL1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee et al. such that the fifth transistor include a silicon-based semiconductor region. and the gate low voltage line is configured to supply the second gate low voltage to a bias electrode of the fifth transistor as taught by Na et al. in order to reduce power consumption.
As to claim 19, Lee et al. teaches the display device of claim 13, but does not explicitly disclose further comprising a plurality of stages configured to supply the first to fourth gate signals,wherein the gate low voltage line is electrically connected to the plurality of stages. However, Na et al. teaches further comprising a plurality of stages configured to supply the first to fourth gate signals ([0096-0100];[0113]: stages), wherein the gate low voltage line is electrically connected to the plurality of stages ([0088];[0092]: scan driving circuit applying scan signals to scan lines; [0113]: stages;[0153]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee et al. with a plurality of stages configured to supply the first to fourth gate signals, wherein the gate low voltage line is configured to supply the second gate low voltage to the plurality of stages as taught by Na et al. in order to apply voltage to the scan lines.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2022/0208930 A1) in view of Na et al. (US 2023/0206847 A1) and further in view of Shin et al. (US 2020/0020263 A1).
As to claim 20, Lee et al. teaches the display device of claim 13, but does not explicitly disclose further comprising a plurality of stages configured to supply the first to fourth gate signals,wherein the gate low voltage line is insulated from the plurality of stages. However, Na et al. teaches comprising a plurality of stages configured to supply the first to fourth gate signals ([0096-0100];[0113]: stages).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee et al. with a plurality of stages configured to supply the first to fourth gate signals as taught by Na et al. in order to apply voltage to the scan lines.
Lee et al. in view of Na et al. teaches the device as discussed above, but does not explicitly disclose wherein the gate low voltage line is insulated from the plurality of stages.
However, Shin et al. teaches wherein the gate low voltage line (G1 in Fig. 5;[0100]: gate line G1) is insulated (140 in Fig. 5; [0101]: insulating layer 140) from the plurality of stages (insulating layer 140 between stage connection line 178 and gate line G1 in Fig. 5;[0062]: stages; [0099];[0101]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee et al. in view of Na et al. such that the gate low voltage line is insulated from the plurality of stages as taught by Shin et al. in order to provide display device including a gate driver capable of facilitating defect inspection of gate line.
Allowable Subject Matter
Claim 5, and 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STACY KHOO whose telephone number is (571)270-3698. The examiner can normally be reached Mon-Fri 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STACY KHOO/Primary Examiner, Art Unit 2624