DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (of record, US 20130214396 A1) in view of Kwon et al. (of record, KR 20130132162 A, machine translation previously provided).
Regarding claim 1, Kim discloses a method of fabricating a semiconductor package (200, Fig. 2), the method comprising:
providing a first die (130) having an active side (bottom) and a backside (top) opposite the active side, the active side having a plurality of die level interconnects (per 132) thereon, and the first die having a first sidewall (left or right) and a second sidewall (the other of left or right) between the active side and the backside, the second sidewall laterally opposite the first sidewall;
coupling a redistribution layer (110+) to the active side (bottom) of the first die;
coupling the redistribution layer to a plurality of package level interconnects (118);
forming a first conductive via structure (one 150s) laterally adjacent to and spaced apart from a first edge (left or right) of the first die, the first conductive via structure coupled to the redistribution layer, and the first conductive via structure extending above the backside (top) of the first die;
forming a second conductive via structure (another 150s) laterally adjacent to and spaced apart from a second edge (the other of left or right) of the first die opposite the first edge of the first die, the second conductive via structure coupled to the redistribution layer, and the second conductive via structure extending above the backside (top) of the first die;
forming a first mold compound (145) in contact with the first sidewall and the second sidewall of the first die;
providing a second die (140a) above the first die, the second die having an active side (top) and a backside (bottom) opposite the active side, the active side of the second die having a plurality of die level interconnects (per wires 142sw/142gw) thereon, the backside (bottom) of the second die facing the backside (top) of the first die;
providing a third die (140b) above the second die, the third die having an active side (top) and a backside (bottom) opposite the active side, the active side of the third die having a plurality of die level interconnects (per wires 142sw/142gw) thereon, the backside (bottom) of the third die facing the active side (top) of the second die;
forming a first wire bond (one of wires 142sw/142gw) coupling one of the plurality of die level interconnects of the second die (140a) to the first conductive via structure;
forming a second wire bond (another one of wires 142sw/142gw) coupling one of the plurality of die level interconnects of the third die (140b) to the second conductive via structure; and
forming a second compound (155) laterally adjacent the second die, the third die, the first wire bond, and the second wire bond, wherein the second compound is further over the active side of the third die (Fig. 2).
Kim fails to disclose forming an electrically insulative material in direct physical contact with the first mold compound, the electrically insulative material having an uppermost surface above a level of the backside of the first die, and the electrically insulative material having a bottommost surface at a same level as a bottommost surface of the first mold compound, wherein the first conductive via structure and the second conductive via structure are within and in contact with the electrically insulative material.
Kwon discloses (Fig. 15) forming an electrically insulative material (110) in direct physical contact with the first mold compound (140), the electrically insulative material having an uppermost surface above a level of the backside (top) of the first die (130), and the electrically insulative material (110) having a bottommost surface at a same level as a bottommost surface of the first mold compound (140), wherein the first conductive via structure (one 120) and the second conductive via structure (another 120) are within and in contact with the electrically insulative material (110, Fig. 15).
PNG
media_image1.png
310
694
media_image1.png
Greyscale
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the arrangement of Kwon in Kim and arrive at the claimed invention so as to form “a semiconductor package including accurate through wiring with a low process defect” (Kwon, Abstract).
Regarding claims 2-5, Kim/Kwon discloses (claim 2) further comprising: forming a spacer (142b which has a thickness and therefore creates a separation) between the backside (bottom) of the third die (140b) and the active side (top) of the second die (140a, Fig. 2), (claim 3) wherein the second compound (155) is laterally adjacent the spacer (142b, Fig. 2), (claim 4) further comprising: forming a first conductive pad (122s/122g or pad on top surface of 120) between the first wire bond (one of wires 142sw/142gw) and the first conductive via structure (one 150s), and a second conductive pad (122s/122g or pad on top surface of 120) between the second wire bond (another one of wires 142sw/142gw) and the second conductive via structure (another 150s, Fig. 2), and, (claim 5) wherein the plurality of package level interconnects (118) of the semiconductor package (200) comprises a first plurality of solder balls below the first die and within a periphery of the first die, and a second plurality of solder balls below the first die and outside of the periphery of the first die (Fig. 2).
Regarding claim 6, Kim discloses a method of fabricating a semiconductor package (200, Fig. 2), the method comprising:
providing a first die (130) having an active side (bottom) and a backside (top) opposite the active side, the active side having a plurality of die level interconnects (per 132) thereon;
forming a redistribution layer (110+), the redistribution layer coupled to the active side of the first die, and the redistribution layer coupled to a plurality of package level interconnects (118);
forming a first via bar (one 150s) laterally adjacent to and spaced apart from a first edge (left or right) of the first die, the first via bar coupled to the redistribution layer, and the first via bar extending above the backside (top) of the first die;
forming a second via bar (another 150s) laterally adjacent to and spaced apart from a second edge (the other of left or right) of the first die opposite the first edge of the first die, the second via bar coupled to the redistribution layer, and the second via bar extending above the backside (top) of the first die;
forming a first encapsulation layer (145) laterally surrounding and in contact with the first die;
providing a second die (140a) above the first die, the second die having an active side (top) and a backside (bottom) opposite the active side, the active side of the second die having a plurality of die level interconnects (per wires depicted) thereon, the backside (bottom) of the second die facing the backside (top) of the first die;
providing a third die (140b) above the second die, the third die having an active side (top) and a backside (bottom) opposite the active side, the active side of the third die having a plurality of die level interconnects (per wires depicted) thereon, the backside (bottom) of the third die facing the active side (top) of the second die;
forming a first wire bond (depicted in Fig. 2) coupling one of the plurality of die level interconnects of the second die to the first via bar;
forming a second wire bond (depicted in Fig. 2) coupling one of the plurality of die level interconnects of the third die to the second via bar; and
forming a second encapsulation layer (155) laterally adjacent the second die, the third die, the first wire bond, and the second wire bond, wherein the second encapsulation layer is further over the active side of the third die (Fig. 2).
Kim fails to disclose forming an electrically insulative material in direct physical contact with the first encapsulation layer, the electrically insulative material having an uppermost surface above a level of the backside of the first die, and the electrically insulative material having a bottommost surface at a same level as a bottommost surface of the first encapsulation layer, wherein the first via bar and the second via bar are within and in contact with the electrically insulative material.
Kwon discloses (Fig. 15) forming an electrically insulative material (110) in direct physical contact with the first encapsulation layer (140), the electrically insulative material having an uppermost surface above a level of the backside (top) of the first die (130), and the electrically insulative material having a bottommost surface at a same level as a bottommost surface of the first encapsulation layer (Fig. 15), wherein the first via bar (120) and the second via bar (120) are within and in contact with the electrically insulative material (110, Fig. 15).
PNG
media_image1.png
310
694
media_image1.png
Greyscale
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the arrangement of Kwon in Kim and arrive at the claimed invention so as to form “a semiconductor package including accurate through wiring with a low process defect” (Kwon, Abstract).
Regarding claims 7 and 8, Kim/Kwon discloses (claim 7) further comprising: forming a spacer (142b) between the backside (bottom) of the third die and the active side (top) of the second die (Fig. 2), and, (claim 8) wherein the second encapsulation layer (155) is laterally adjacent the spacer (Fig. 2).
Regarding claim 9, Kim/Kwon discloses (Fig. 2) further comprising: forming a first conductive pad (at top or bottom of 120) between the first wire bond and the first via bar; and forming a second conductive pad (another at top or bottom of 120) between the second wire bond and the second via bar (Fig. 2).
Regarding claims 10-12, Kim/Kwon discloses (claim 10) wherein the plurality of package level interconnects (118) comprises a plurality of solder balls (“solder ball 118”) below the first die and outside of a periphery of the first die (Fig. 2), (claim 11) wherein the plurality of package level interconnects (118) comprises a plurality of solder balls (“solder ball 118”) below the first die and within a periphery of the first die (Fig. 2), and (claim 12) wherein the plurality of package level interconnects (“solder ball 118”) comprises a first plurality (inner) of solder balls below the first die and within a periphery of the first die, and a second plurality (outer) of solder balls below the first die and outside of the periphery of the first die (Fig. 2).
Regarding claim 13, Kim/Kwon discloses further comprising: forming a second redistribution layer (e.g., 116 and/or 112s) between the redistribution layer (as upper 110+) and the plurality of package level interconnects (118, Fig. 2).
Regarding claim 14, Kim/Kwon discloses wherein the second die (140a) and the third die (140b) are vertically aligned with one another (Fig. 2).
Regarding claim 15, Kim/Kwon discloses wherein the first encapsulation layer (145) has an uppermost surface above the backside of the first die (130, Fig. 2).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (of record, US 20130214396 A1) in view of Kwon et al. (of record, KR 20130132162 A, machine translation previously provided) as applied to claim 6 above, and further in view of Chen et al. (of record, US 20130221522 A1).
Regarding claim 13, under an alternative interpretation, Kim/Kwon fails to disclose further comprising: forming a second redistribution layer between the redistribution layer and the plurality of package level interconnects.
Chen discloses (Fig. 1C) further comprising: forming a second redistribution layer (one B*) between the redistribution layer (another B*) and the plurality of package level interconnects (125, [0024] – “Package 120 also includes a redistribution region B*, which also have interconnect structures, such as one or more redistribution layers (RDLs) that make connections between the semiconductor die in the package with connectors 125”, emphasis added).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include multiple RDLs in Kim/Kwon per Chen so as to facilitate means to electrically address all the dies within a package via, e.g., fanning out of interconnections of said dies, and/or because it has been held that duplication parts of an invention is generally recognized as being within the level of ordinary skill in the art (MPEP 2144.04 VI).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (of record, US 20130214396 A1) in view of Kwon et al. (of record, KR 20130132162 A, machine translation previously provided) as applied to claim 6 above, and further in view of Yu et al. (of record, US 20130093097 A1).
Regarding claim 16, Kim/Kwon fails to disclose further comprising: providing a fourth die having an active side coupled to a die side of the redistribution layer.
Yu discloses further comprising: providing a fourth die (62, fourth counting those of Kim/Chow) having an active side (next to 64) coupled to a die side of the redistribution layer (26+, Fig. 15).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include a fourth die in Kim/Kwon in between solder balls 118 of Kim in view of Yu and arrive at the claimed invention so as to expand functionality of a package by including a thin IC in between solder balls and/or so as to add a memory die (Yu, [0033]).
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (of record, US 20130214396 A1) in view of Kwon et al. (of record, KR 20130132162 A, machine translation previously provided) and Chow et al. (of record, US 20100144101 A1).
Regarding claim 17, Kim discloses (Fig. 2) a method of fabricating an integrated circuit (IC) assembly, the method comprising:
forming a semiconductor package (Fig. 2), comprising:
a first integrated circuit (130) having an active side (bottom) and a backside (top) opposite the active side, the active side having a plurality of die level interconnects (per 132) thereon;
a redistribution layer (110+), the redistribution layer coupled to the active side of the first integrated circuit, and the redistribution layer coupled to a plurality of package level interconnects (118);
a first via bar (one 150s) laterally adjacent to and distanced apart from a first edge of the first integrated circuit, the first via bar coupled to the redistribution layer, and the first via bar extending above the backside of the first integrated circuit;
a second via bar (another 150s) laterally adjacent to and distanced apart from a second edge of the first integrated circuit opposite the first edge of the first integrated circuit, the second via bar coupled to the redistribution layer, and the second via bar extending above the backside of the first integrated circuit;
a first encapsulation layer (145) laterally surrounding and in contact with the first integrated circuit;
a second integrated circuit (140a) above the first integrated circuit, the second integrated circuit having an active side (top) and a backside (bottom) opposite the active side, the active side of the second integrated circuit having a plurality of integrated circuit level interconnects (per wires shown) thereon, the backside of the second integrated circuit facing the backside of the first integrated circuit;
a third integrated circuit (140b) above the second integrated circuit, the third integrated circuit having an active side (top) and a backside (bottom) opposite the active side, the active side of the third integrated circuit having a plurality of integrated circuit level interconnects (per wires shown) thereon, the backside of the third integrated circuit facing the active side of the second integrated circuit;
a first wire bond (shown) electrically connecting one of the plurality of integrated circuit level interconnects of the second integrated circuit to the first via bar;
a second wire bond (another shown) electrically connecting one of the plurality of integrated circuit level interconnects of the third integrated circuit to the second via bar; and
a second encapsulation layer (155) laterally adjacent the second integrated circuit, the third integrated circuit, the first wire bond, and the second wire bond, wherein the second encapsulation layer is further over the active side of the third integrated circuit; and
coupling a circuit board ([0054], “mother board”) to the semiconductor package,
Kim fails to disclose (i) an electrically insulative material in direct physical contact with the first encapsulation layer, the electrically insulative material having an uppermost surface above a level of the backside of the first integrated circuit, and the electrically insulative material having a bottommost surface at a same level as a bottommost surface of the first encapsulation layer, wherein the first via bar and the second via bar are within and in contact with the electrically insulative material, and, (ii) the circuit board having a plurality of electrical routing features disposed therein and a plurality of pads disposed thereon, wherein the plurality of pads are electrically coupled with the plurality of package level interconnects.
Kwon discloses (i) (Fig. 15) an electrically insulative material (110) in direct physical contact with the first encapsulation layer (140), the electrically insulative material having an uppermost surface above a level of the backside (top) of the first integrated circuit (130), and the electrically insulative material having a bottommost surface at a same level as a bottommost surface of the first encapsulation layer (Fig. 15), wherein the first via bar (120) and the second via bar (120) are within and in contact with the electrically insulative material (Fig. 15).
PNG
media_image1.png
310
694
media_image1.png
Greyscale
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the arrangement of Kwon in Kim and arrive at the claimed limitation in question so as to form “a semiconductor package including accurate through wiring with a low process defect” (Kwon, Abstract).
Chow discloses (ii) the circuit board (12) having a plurality of electrical routing features disposed therein ([0026] – “Conductive signal traces 14 are formed on a surface or within layers of PCB 12”; emphasis added) and a plurality of pads (64, [0030]) disposed thereon, wherein the plurality of pads are electrically coupled with the plurality of package level interconnects (66, Fig. 2b).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the arrangement of Chow in Kim/Kwon so as to enable mounting of packages onto a higher level integrated device (e.g., a computer).
Regarding claims 18 and 19, Kim/Kwon/Chow discloses (claim 18) wherein the semiconductor package includes a processor (DSP, [0031]), and, (claim 19) wherein the semiconductor package includes a memory ([0031], volatile/nonvolatile).
Regarding claim 20, Kim/Kwon/Chow discloses wherein the semiconductor package further comprises a spacer (142b) between the backside (bottom)of the third integrated circuit and the active side (top) of the second integrated circuit (Fig. 2).
Response to Arguments
Applicant's arguments filed 4.10.2026 have been fully considered but they are not persuasive.
The applicant alleges “…the combination of Kim in view of Kwon does not disclose a method of fabricating a semiconductor package, the method including forming a first mold compound in contact with a first sidewall and a second sidewall of a first die, and forming an electrically insulative material in direct physical contact with the first mold compound, the electrically insulative material having an uppermost surface above a level of the backside of the first die, and the electrically insulative material having a bottommost surface at a same level as a bottommost surface of the first mold compound, as is required by Applicant's claims. As such, with respect to amended independent claims 1, 6 and 17, the combination of Kim in view of Kwon fails to disclose each and every feature of Applicant's claims”. Applicant includes the annotated figure below.
PNG
media_image2.png
322
610
media_image2.png
Greyscale
The examiner notes that Fig. 15 annotated by the applicant does not correspond to Kwon et al. (KR 20130132162 A). The correct Fig. 15 is included below and applicant’s arguments are not persuasive.
PNG
media_image3.png
188
372
media_image3.png
Greyscale
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Andres Munoz/ Primary Examiner, Art Unit 2818
Prosecution Insights