DETAILED ACTION
Status of Application
Claims 1-23 are pending in the present application.
Response to Arguments
Applicant's arguments filed 07/09/2026 have been fully considered but they are not persuasive, for the reasons set forth below.
Applicant argues: (1) “prefetching accuracy” is “a measure of whether prefetched data is utilized by (i.e., accessed by) that CPU core, e.g., before the prefetched data is evicted from the cache” [remarks, pp. 7-8] and that Cai’s PBPA measures whether branch predictions were accurate and not whether prefetching was accurate in the sense of whether prefetched data was actually utilized by the CPU core [remarks, p, 8]; (2) the prefetching accuracy of claim 1 is fundamentally different from “branch prediction accuracy” since “prefetching accuracy” measures whether data that was speculatively prefetched into cache memory was actually accessed before being evicted [remarks, p. 8]; (3) Cai’s use of branch prediction accuracy is fundamentally different from controlling prefetching based on how accurate past prefetching has been [remarks, p, 8]; (4) Claims 7, 8, 18, and 19 are patentable over the cited prior art [remarks, pp. 9-10].
The examiner respectfully disagrees with these arguments.
In regard to the first argument, the examiner notes that the features upon which applicant relies (i.e., “a measure of whether prefetched data is utilized by (i.e., accessed by) that CPU core, e.g., before the prefetched data is evicted from the cache” [remarks, p. 7] is not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). In addition, it has been held that although a claim should be interpreted in light of the specification disclosure, it is generally considered improper to read limitations contained in the specification into the claims. See In re Prater, 415 F.2d 1393, 162 USPQ 541 (CCPA 1969) and In re Winkhaus, 527 F.2d 637, 188 USPQ 129 (CCPA 1975), which discuss the premise that one cannot rely on the specification to impart limitations to the claim that are not recited in the claim.
The examiner notes that since “prefetching accuracy” is not defined in the claims and since limitations from the specification are not read into the claims, applicant’s argument is not persuasive. If applicant wishes for the examiner to interpret the term “prefetching accuracy” as recited in the Specification, the examiner recommends amending the claims to incorporate paragraph 25 of the Specification.
In regard to the second argument, the examiner notes that the features upon which applicant relies (i.e., “measures whether data that was speculatively prefetched into cache memory was actually accessed before being evicted”) [remarks, p. 8] is not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). In addition, it has been held that although a claim should be interpreted in light of the specification disclosure, it is generally considered improper to read limitations contained in the specification into the claims. See In re Prater, 415 F.2d 1393, 162 USPQ 541 (CCPA 1969) and In re Winkhaus, 527 F.2d 637, 188 USPQ 129 (CCPA 1975), which discuss the premise that one cannot rely on the specification to impart limitations to the claim that are not recited in the claim.
In addition, Cai discloses that the PBPA field “represents a history of whether past predictions of the branch instruction were accurate” [Cai, col. 13, lines 55-56]. The claims are given the broadest reasonable interpretation in regard to “prefetching accuracy,” therefore the examiner is not persuaded by applicant’s argument.
Regarding the third argument, the examiner notes that claim 1 does not elaborate on the term “prefetching accuracy,” hence applicant’s argument that Cai is fundamentally different than “controlling prefetching based on how accurate past prefetching has been” [remarks, p. 8] is not persuasive. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). The examiner does not see any claim language stating that prefetching accuracy is related to how accurate past prefetching has been. Assuming arguendo, that prefetching accuracy is equivalent to how accurate past prefetching has been, Cai states “the past prediction accuracy field PBPA represents a history of whether past predictions of the branch instruction were accurate” [Cai, col. 13, lines 55-56]. Hence, PBPA representing a history of whether past predictions of the branch instruction were accurate and prefetching accuracy indicating how accurate past prefetching has been, are of the same meaning. Applicant argues that the value indicative of the prefetching accuracy indicates “whether previously prefetched data was actually utilized, a feedback mechanism that adjust prefetching behavior based on the effectiveness of the prefetching itself” [remarks, p. 9]. However, as previously mentioned, the features upon which applicant relies (i.e., “whether previously prefetched data was actually utilized, a feedback mechanism that adjust prefetching behavior based on the effectiveness of the prefetching itself” is not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Regarding the fourth argument, applicant has not provided specific arguments as to how claims 7, 8, 18, and 19 are patentably distinguishable from the references. Therefore, the prior art rejection of claims 7, 8, 18, and 19 is maintained.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 12, and 23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cai et al (hereinafter Cai), US 6029228.
Referring to claims 1, 12, and 23, taking claim 1 as exemplary, Cai discloses a computing system, comprising:
a processor comprising a Central Processing Unit (CPU) core [fig. 1, microprocessor 12] and a cache memory for the CPU core [col. 3, lines 25-33, “Still another prior art technique for increasing speed involves the prefetching of information in combination with cache systems. Prefetching involves a speculative retrieval, or preparation to retrieve, information, where the information is retrieved from a higher level memory system, such as an external memory, into a cache under the expectation that the retrieved information may be needed by the microprocessor”];
wherein the CPU core is configured to:
generate a value indicative of a prefetching accuracy of the CPU core [col. 13, lines 36-39, “entry 41 in BTB 41 also includes a value designated PBPA which indicates a past branch prediction accuracy measure for past occurrences of the branch instruction”; col. 13, lines 51-54, “In any event, returning to the value designated PBPA, recall the prediction value P represents a history of whether, in fact, past occurrences of the branch instruction were taken”] for prefetching of data [col. 14, lines 49-53, “PBPA is one of three different values which may be used to determine whether a prefetch request should be issued for a data fetching instruction which follows the branch instruction having the value of PBBA”], instructions, or both data and instructions from system memory external to the processor for storage in the cache memory for the CPU core [col. 3, lines 25-33, “involves the prefetching of information in combination with cache systems. Prefetching involves a speculative retrieval, or preparation to retrieve, information, where the information is retrieved from a higher level memory system, such as an external memory, into a cache under the expectation that the retrieved information may be needed by the microprocessor”]; and
control the prefetching performed by the CPU core based on the value indicative of the prefetching accuracy [col. 14, lines 49-53, “PBPA is one of three different values which may be used to determine whether a prefetch request should be issued for a data fetching instruction which follows the branch instruction having the value of PBBA”].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cai et al (hereinafter Cai), US 6029228, in view of Morrow et al (hereinafter Morrow), US 20090019229 A1.
Referring to claims 7 and 18, taking claim 7 as exemplary, Cai does not explicitly disclose the computing system of claim 1, wherein, in order to control the prefetching of the CPU core, the CPU core is further configured to:
determine, based on the value indicative of the prefetching accuracy, that the prefetching accuracy of the CPU core is less than a first prefetching accuracy threshold; and
in response to determining that the prefetching accuracy of the CPU core is less than the first prefetching accuracy threshold, partially deactivate the prefetching of the CPU core.
However, Morrow discloses determine, based on the value indicative of the prefetching accuracy, that the prefetching accuracy of the CPU core is less than a first prefetching accuracy threshold [claim 20]; and
in response to determining that the prefetching accuracy of the CPU core is less than the first prefetching accuracy threshold, partially deactivate the prefetching of the CPU core [claim 20, “wherein the cache controller disables data prefetching for the data cache if the prefetch hit rate falls to a defined disable threshold as indicated by the value of the first counter”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Morrow in the system of Cai, to implement wherein, in order to control the prefetching of the CPU core, the CPU core is further configured to: determine, based on the value indicative of the prefetching accuracy, that the prefetching accuracy of the CPU core is less than a first prefetching accuracy threshold; and in response to determining that the prefetching accuracy of the CPU core is less than the first prefetching accuracy threshold, partially deactivate the prefetching of the CPU core, in order to eliminate prefetching overhead and preventing the pollution of the data cache 106 with data lines that probably will not be used [Morrow, paragraph 22].
Claim(s) 8 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cai, in view of Morrow, as applied to claims 7 and 18 above, and further in view of Rotithor et al (hereinafter Rotithor), US 20040123043 A1.
Referring to claims 8 and 19, taking claim 8 as exemplary, the modified Cai does not explicitly disclose the computing system of claim 7, wherein, when prefetching is partially deactivated, the CPU core issues fewer prefetching requests than when prefetching is activated.
However, Rotithor discloses wherein, when prefetching is partially deactivated, the CPU core issues fewer prefetching requests than when prefetching is activated [paragraph 20, “the arbiter 260 inserts 320 prefetches aggressively at a particular instant if the MBU rate is above an MBU threshold value and the PBHR is above a PBHR threshold value. The arbiter 260 inserts 330 prefeteches conservatively if the MBU rate is above the MBU threshold value and the PBHR is below the PBHR threshold value”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Rotithor in the system of the modified Cai, to implement wherein, when prefetching is partially deactivated, the CPU core issues fewer prefetching requests than when prefetching is activated, in order to efficiently predicting future read accesses utilizing the memory device-state (e.g., DRAM-state) information, and adjusting prefetch injection based on how well the prefetches injected previously are being used by subsequent reads [Rotithor, paragraph 35].
Allowable Subject Matter
Claims 2-6, 9-11, 13-17, and 20-22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein the value indicative of the prefetching accuracy of the CPU core is an unsigned saturating counter value, and the CPU core generates the value indicative of the prefetching accuracy of the CPU core by adjusting the unsigned saturating counter value by a first value for each instance of a prefetching line fill in which a prefetched memory line is stored in the cache memory for the CPU core and adjusting the unsigned saturating counter value by a second value for each instance of a hit on a prefetched memory line in the cache memory, in combination with other recited limitations in claim 2.
Claims 3-6 are objected to by virtue of their dependency.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein the CPU core is further configured to: update the value indicative of the prefetching accuracy of the CPU core while the prefetching is partially deactivated; determine, based on the updated value, that the prefetching accuracy of the CPU core has increased to or above a second prefetching accuracy threshold for activating the prefetching of the CPU core; and in response to determining that the prefetching accuracy of the CPU core has 30 increased to or above the second prefetching accuracy threshold, activate the prefetching of the CPU core, in combination with other recited limitations in claim 9.
Claims 10-11 are objected to by virtue of their dependency.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein the value indicative of the prefetching accuracy of the CPU core is an unsigned saturating counter value, and generating the value indicative of the prefetching accuracy of the CPU core comprises: adjusting the unsigned saturating counter value by a first value for each instance of a prefetching line fill in which a prefetched memory line is stored in the cache memory for the CPU core; and adjusting the unsigned saturating counter value by a second value for each instance of a hit on a prefetched memory line in the cache memory, in combination with other recited limitations in claim 13.
Claims 14-17 are objected to by virtue of their dependency.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest updating the value indicative of the prefetching accuracy of the CPU core while the prefetching is partially deactivated; determining, based on the updated value, that the prefetching accuracy of the CPU core has increased to or above a second prefetching accuracy threshold for activating the prefetching of the CPU core; and in response to determining that the prefetching accuracy of the CPU core has increased to or above the second prefetching accuracy threshold, activating the prefetching of the CPU core, in combination with other recited limitations in claim 20.
Claims 21-22 are objected to by virtue of their dependency.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARLEY J ABAD whose telephone number is (571)270-3425. The examiner can normally be reached Mon-Fri 8:30 AM - 7 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Farley Abad/ Primary Examiner, Art Unit 2181
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