DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim(s) 5, 14 and 19 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein the input buffer is configured to convert the first frequency to the second frequency; while in regard to claim 14, the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein the input buffer is configured to convert the first frequency to the second frequency; while in regard to claim 19, the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein a source of the data is clocked at a first frequency, wherein the CIM module is clocked at a second frequency, the input buffer is configured to convert the first frequency to the second frequency, the first frequency being a multiple of the second frequency.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2 and 17 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 20250210078 to Sun et al. (“Sun”).
As to claim 1, Sun teaches A compute engine (CE) (As found in at least [0002]), comprising: a compute-in-memory (CIM) module including a plurality of storage cells and compute logic coupled with the plurality of storage cells (As found in at least [0002]: CIM integrates processing capabilities with memory arrays), the plurality of storage cells being arranged in a plurality of rows and a plurality of columns (As found in at least FIG. 2: CIM 110 arranged in rows and columns); and an input buffer coupled with the CIM module and configured to receive data, reshape the data, and provide reshaped data to the CIM module (As found in at least FIG. 1: there are at least 3 buffers 102, 104 and 120 coupled to CIM 110; they provide data to CIM; data from buffer to CIM reshaped (unless the Application requires and claims an specific data reshaping type, the claim is given a broadest and reasonable meaning) as found in at least claim 19).
As to claim 2, Sun teaches wherein the input buffer includes a plurality of shift registers configured to bit-wise transpose the data (As found in at least FIG. 1, buffer 102 may include directly connected fetch circuit 106; and as found in at least [0034], data shifting is accomplished).
As to claim 17, see rejection to at least claim 1; moreover, the method is inherently taught by the apparatus.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 7-8, 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20250210078 to Sun et al. (“Sun”) in view of KR 20190017112 A to Lee et al. (“Lee”).
As to claim 3, while Sun teaches substantially the claimed invention including the claimed buffer coupled to the claimed CIM, Sun may not expressly teach wherein the data is bit-parallel and the input buffer bit-serializes the data.
Yet, relevantly and complementarily, Lee teaches wherein the data is bit-parallel and the input buffer bit-serializes the data (As found in at least under DESCRIPTION-OF-EMBODIMENTS: “The input / output data buffer 270 may convert the parallel data bits output from the first through fourth bank arrays 240A through 240D to serial data bits.”).
Sun and Lee are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: storage devices having data buffers.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Sun as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Lee also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: it is well-known and well-understood in the relevant art circuitry that is arranged to either or even both data convert from parallel to serial or serial to parallel. Lee provides just an example of such well-kwon circuit implementation.
Therefore, it would have been obvious to combine Sun with Lee to make the above modification.
As to claim 7, see rejection to at least claim 3, moreover, Lee teaches wherein the input buffer includes at least one bank and wherein a portion of the data in each of the at least one bank is loaded to the CIM module in parallel (As found in at least under DESCRIPTION-OF-EMBODIMENTS: “The input / output data buffer 270 includes first to fourth bank arrays 240A to 240D”).
As to claim 8, Lee teaches further comprising: a demultiplexer configured to route a portion of the data to a bank of the at least one bank (As found in at least FIG. 1: buffer 270 is part of a system that also includes BANKS 240A-240D; there must necessarily be a means of demuxing the Banks from the buffer to avoid data collision).
As to claim 18, see rejection to at least claim(s) 2-3.
As to claim 20, see rejection to at least claim 7.
Claim(s) 4 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20250210078 to Sun et al. (“Sun”) in view of CN 115910159 A to Li et al. (“Li”).
As to claim 4, at least Li teaches wherein a source of the data is clocked at a first frequency and the CIM module is clocked at a second frequency (As found in at least the Abstract, and at least under Description: “In some embodiments, the frequency of the clock signal CLK1 is equal to or less than the MAC operation speed;” where, CLK1 is the CIM clock frequency and the MAC operation speed is that of the source).
Sun and Li are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: storage devices having data buffers.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Sun as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Li also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: as found in Li: “When the MAC operation speed is lower than the clock frequency in the CIM macro 110 that performs the MAC operation, the CIM macro 110 cannot correctly perform the accumulation function, resulting in an error in the MAC operation.” That is, the source clock must be faster than the CIM clock.
Therefore, it would have been obvious to combine Sun with Li to make the above modification.
As to claim 6, see rejection to at least claim 4; note that a “multiple” is a broad term and can encompass any value including integer and non-integer numbers.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20250210078 to Sun et al. (“Sun”) in view of US 20250238482 to Hadidi et al. (“Hadidi”).
As to claim 9, see rejection to at least claim 1; moreover, Hadidi further complements with teaching of a compute tile, comprising: at least one general-purpose (GP) processor; and a plurality of compute engines (CEs), each of the plurality of CEs including a compute- in-memory (CIM) module (As found in at least FIG. 1: processor 110, CE 120-1 that includes CIM 130-1, 130-2).
Sun and Hadidi are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: storage devices having data buffers.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Sun as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Hadidi also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: it is well-known and well-understood, made evident by the anticipatory teachings of Hadidi, that CIM modules do not exist in a vacuum; to be operational they need to be part of a system that may include more than just processors and CEs.
Therefore, it would have been obvious to combine Sun with Hadidi to make the above modification.
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20250210078 to Sun et al. (“Sun”) in view of US 20250238482 to Hadidi et al. (“Hadidi”), and further in view of in view of KR 20190017112 A to Lee et al. (“Lee”).
As to claim(s) 10-11, see rejection to at least claim 3.
Claim(s) 12-13 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20250210078 to Sun et al. (“Sun”) in view of US 20250238482 to Hadidi et al. (“Hadidi”), and further in view of CN 115910159 A to Li et al. (“Li”).
As to claim 12, see rejection to at least claim 4.
As to claim 13, at least Hadidi teaches wherein the source of the data is the at least one GP io processor (As found in at least FIG. 1: processor 110 sources data/signal/command/etc. to CE).
As to claim 15, see rejection to at least claim 6.
As to claim 16, see rejection to at least claim 7.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
At least Claim(s) 1, 9 and 17 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over at least claim(s) 1, 9 and 17 of copending Application No. 19/034331 (US 2025/0321685) (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are obviated by the co-pending Application claims. A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over (in a non-statutory double patent rejection) the earlier claim. In re Lonqi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Bercl, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). Ely Lilly and Co. v Bar Laboratories, Inc., United States Court of Appeals for the Federal Circuit, on petition for rehearing en banc (decided: May 30, 2001).The instant claims are obviated by the co-pending claims; the co-pending Applicaiton and the application claim obvious common subject matter: A compute engine, a compute tile, a method, comprising, in brief and saliently: a compute-in-memory (CIM) module including a plurality of storage cells and compute logic coupled with the plurality of storage cells, the plurality of storage cells being arranged in a plurality of rows and a plurality of columns; and an input buffer coupled with the CIM module and configured to receive data (weights, input vector), and provide data to the CIM.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827
Prosecution Insights