DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim(s) 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein the at least one memory includes at least one voltage regulating circuit adjusting the read voltage to be output to at least one of the plurality of bank groups, based on the voltage level table.
Claim(s) 10-13 depend from claim 9 and as such are also objected for the same reasons.
Allowable Subject Matter
Claim(s) 14-18 are allowed.
The following is an examiner’s statement of reasons for allowance: the pertinent prior art of record, and in light of such record as a whole under MPEP 1302.14 guidance, and further guidance under MPEP 2103, in brief and saliently: “the claim as a whole must be considered,” does not teach or suggest the combination of claim limitations making the whole of the claim(s) of the claimed invention, particularly as set forth in representative claim(s) 14.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-8 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by US 20220336036 to Lee et al. (“Lee”).
As to claim 1, Lee teaches an electronic device (As found in at least FIG. 1) comprising: at least one memory including a plurality of bank groups (As found in at least FIGS. 1-2: bank or block groups BLK1-BLKz; or alternatively as found in at least FIG. 13); and a controller (As found in at least FIGS. 1-2 and 13) configured to: update a history table including a level value indicating a read voltage for a read operation on the plurality of bank groups based on fail bit information according to an error correction operation for data read from the at least one memory, and transmit the level value included in the updated history table to the at least one memory (As found in at least Claims 1 and 11 and at least [0108]).
As to claim 2, Lee teaches wherein, when a read request is received, the controller identifies the level value included in the history table, transmits an active command including the level value to the at least one memory, and then transmits a read command corresponding to the read request to the at least one memory (As found in at least FIG. 1: memory 100 responds to Controller 200 commands; also, refer to at least [0038]; moreover, see rejection to at least claim 1).
As to claim 3, Lee teaches wherein the controller transmits the level value to the at least one memory through at least some bits included in an active command (See rejection to at least claim 1; moreover, refer to at least [0042]).
As to claim 6, Lee teaches wherein the fail bit information includes a number of fail bits or a ratio of the fail bits, and the controller adjusts the level value according to at least one of the number of fail bits, the ratio of the fail bits, a variation width of the number of the fail bits, or a variation width of the ratio of the fail bits (As found in at least the Abstract: error bit information on each of a plurality of memory blocks; that is a number of fail bits; the controller determines whether the history read table is to be updated by comparing the root bit information of the read retry operation with the root bit information of the history read table).
As to claim 7, Lee teaches wherein the controller includes a non-volatile memory storing the history table (As found in at least FIG. 11 and at least [0123]: controller 1300 includes non-volatile ROM for storing various information for the memory operation).
As to claim 8, Lee teaches wherein the at least one memory stores a voltage level table including the read voltage corresponding to the level value (As found in at least the Abstract: The memory device stores a history read table).
As to claim 19, see rejection to at least claim 1.
As to claim 20, Lee teaches wherein the external memory includes a volatile memory, and the internal memory includes a non-volatile memory (External memory RAM in FIG. 11, and internal memory non-volatile in FIG. 3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by US 20220336036 to Lee et al. (“Lee”), and further in view of US 20230420039 to Hoh (“Noh”).
As to claim 4, at least Noh teaches wherein the controller transmits the level value to the at least one memory through a mode register command (While Lee teaches the claimed controller controlling through a bus the memory, Noh teaches such controlling is through a mode register as found in at least [0050] and [0074]).
Lee and Noh are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: devices having memory controllers and memory.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Lee as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Noh also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: as set forth in at least [0050] in Noh, mode registers may include a plurality of mode registers for setting various operation modes of the memory; this clearly provides an advantage: memory operations set at a register.
Therefore, it would have been obvious to combine Lee with Noh to make the above modification.
Claim(s) 5 is/are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by US 20220336036 to Lee et al. (“Lee”), and further in view of US 20240160388 to Song et al. (“Song”).
As to claim 5, at least Song teaches wherein the controller transmits the level value to the at least one memory through a data pattern transmitted before or after transmitting an active command (As found in at least [0017]).
Lee and Song are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: devices having memory controllers and memory.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Lee as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Song also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: as set forth in at least [0017] in Song, data pattern may be used in memory controller communications with a memory; this clearly provides an advantage: data pattens can be predefined in advance.
Therefore, it would have been obvious to combine Lee with Song to make the above modification.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 5712721852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827
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