DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim(s) 8 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, because the specification, while being enabling for switching circuits, does not reasonably provide enablement for wherein the switching circuits connects each of the plurality of word lines with one voltage regulator, among the plurality of voltage regulators. The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention commensurate in scope with these claims. FIG. 2 of the drawings of the present Application seems relevant. For example, WLn connects to regulators 151, 152 and 153. This contradicts the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 15 is/are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by KR 20100107176 A to Suk (“Suk”).
As to claim 1, Suk teaches A memory device (As found in at least FIG. 21:10; and/or FIG. 2: 200) comprising: a memory cell array including memory cells (As found in at least FIGS. 2-3), the memory cells connected through a plurality of word lines (As found in at least FIGS. 2-3); a peripheral circuit configured to apply pass voltages to the plurality of word lines (As found in at least FIG. 2: peripheral circuit 220/250; also, see at least under Detail Description: “The address decoder 220 operates under the control of the control logic 250. The address decoder 220 receives an address ADDR from the outside. In exemplary embodiments, the address ADDR may be transmitted from the controller 100 of FIG. 1. The address decoder 220 selects word lines WL by decoding a row address among the transferred addresses ADDR. Through the selected word lines, voltages for a program operation, voltages for a read operation, or voltages for an erase operation will be biased to the memory cell array 210; also, see at least FIG. 6: word lines WL are applied a pass voltage) and, after applying the pass voltages to the plurality of word lines, configured to apply a program voltage to a select word line (As found in at least FIG. 6: selected WL6 is applied a program voltage after a pass voltage), selected among the plurality of word lines, in a period in which a program operation is performed (As found in at least FIG. 6: selected WL6 is applied a program voltage after a pass voltage), wherein the pass voltages include a first pass voltage and a second pass voltage (As found in at least FIG. 6: pass voltage includes Vpass1 and Vpass2), and wherein the second pass voltage is higher than the first pass voltage (As found in at least FIG. 6: Vpass2 is higher than Vpass1); and a control logic configured to, during a pass voltage increase period in which the pass voltages are applied, control the peripheral circuit so that the second pass voltage is applied to the select word line and the first pass voltage is applied to unselect word lines (As found in at least FIG. 6: second pass voltage Vpass2 is applied to selected word line W6, and first pass voltage Vpass1 is applied to at least plurality of word lines WL1 and WL2), the unselect word lines being word lines, among the plurality of word lines, which are not selected (As found in at least FIG. 6: unselected word lines are other than selected word line WL6).
As to claim 15, see rejection to at least claim 1; moreover, the method is inherently taught by the apparatus.
Claim(s) 2-6 and 16-18 is/are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over KR 20100107176 A to Suk (“Suk”).
As to claim 2, Suk at the very least obviates wherein the peripheral circuit comprises: a voltage generator including a first pass voltage regulator generating the first pass voltage and a second pass voltage regulator generating the second pass voltage; and an address decoder connecting a plurality of voltage regulators included in the voltage generator with the plurality of word lines (As found in at least FIG. 6, Vpass1 and Vpass2 are applied to word lines WL, word lines which are coupled to peripheral circuit 220/250/230 in FIG. 2; while at least FIG. 21 provides that 300 which includes memory 10 also includes a power supply 340, operable to provide voltages to apply to at least word lines; while at least FIG. 2 teaches an address decoder 220 coupling word lines WL to voltage means).
It would have obvious to one of very ordinary skill in the art before the effective filing date of the present application to recognize that application of any voltages to memory require a means to generate such voltages, or acquire such voltages.
As to claim 3, Suk teaches in an obvious manner: wherein the control logic generates a first control signal for applying the pass voltages to the corresponding word lines, among the plurality of word lines, during the pass voltage increase period, and wherein the address decoder connects the first pass voltage regulator with the unselect word lines and connects the second pass voltage regulator with the select word line in response to the first control signal (As found in at least FIGS. 2-3 and 6; also see rejection to at least claim 2).
As to claim 4, see rejection to at least claim 3; whether it is applying pass voltage or program voltages to word lines, these are obviously operable by means of 220/250/230 in FIG. 2 and 340 in FIG. 21.
As to claim 5, Suk teaches wherein the address decoder connects the select word line with the program voltage regulator in response to the second control signal (As found in at least FIG. 2: address decoder 220 connects word lines WL with voltage regulators 250; also, see at least under Detail Description: “In exemplary embodiments, the program controller 251 may control the first pass voltage Vpass1 to be applied to the word lines WL1 to WLn”).
As to claim 6, Suk teaches in an obvious manner: wherein the address decoder maintains a connection between the first pass voltage regulator and the unselect word lines and releases a connection between the second pass voltage regulator and the select word line (As found in at least FIG. 6, Vpass1 is connected to unselected WL, while in order to provide Vpgm to the selected WL, Vpass2 must be released; should this not be obvious, Vpgm and Vpass2 would short on selected WL).
As to claim 16, see rejection to at least claim 2.
As to claim 17, Suk obviates the claim: wherein applying the second pass voltage further comprises applying the first pass voltage to unselect word lines, the unselect word lines being word lines, among the plurality of word lines, which are not selected during the pass voltage increase period (As found in at least FIG. 6: applying Vpass2 comprises applying Vpass1 to unselected word lines such as WL1).
As to claim 18, Suk obviates the claim: wherein applying the program voltage further comprises releasing a connection between the second pass voltage regulator and the select word line (As found in at least FIG. 6: applying Vpgm comprises releasing second pass voltage VPass2; Vpass2 and Vpgm, evidently, are not shown active at the same time: to prevent a short between the two).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 and 9-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over KR 20100107176 A to Suk (“Suk”) in view of U.S. Patent/Publication No. 9761313 to Lee (“Lee”) and US 8248842 to Cho et al. (“Cho”).
As to claim 7, while Suk teaches an address decoder 220 in FIG. 2, Suk may not expressly teach wherein the address decoder includes switching circuits connecting the plurality of voltage regulators with the plurality of word lines, respectively.
Yet, relevantly and complementarily, Lee and Cho teach wherein the address decoder includes switching circuits connecting the plurality of voltage regulators with the plurality of word lines, respectively (As found in at least FIG. 1 of Lee, there is taught an address decoder 120 coupled to a voltage generator 150 to drive word lines WL; while Cho in at least FIG. 3 teaches such address decoder includes switching circuits connecting the word lines to different driving signals).
Suk and Lee and Cho are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory having address decoders.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Suk as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Lee and Cho also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: memory arrays include memory cells coupled to word lines and bit lines; word lines and bit lines are driven by address decoders that address a single cell or plurality of cells according to physical addresses; the addresses are wiring lines that carry current/voltage operable to bias the cells; Suk, Lee and Cho make this painfully obvious.
Therefore, it would have been obvious to combine Suk with Lee and Cho to make the above modification.
As to claim 9, see rejection to at least claim 7; moreover, Suk further teaches a pass voltage increase period in which pass voltages are applied to the plurality of word lines (As found in at least FIG. 6).
As to claim 10, Suk teaches wherein the control logic generates a first control signal for applying the first and second pass voltages to the corresponding word lines, among the plurality of word lines, during the pass voltage increase period (As found in at least FIGS. 2 and 21, control logic to apply first and second pass voltages Vpass1 and Vpass2 to corresponding word lines).
As to claim 11, Suk teaches in an obvious manner wherein the switching circuits connect the first pass voltage regulator with the unselect word lines and connect the second pass voltage regulator with the select word line in response to the first control signal (As found in at least FIGS. 2, 6 and 21: first pass voltage Vpass1is connected to unselected word lines such as WL1, and Vpass2 is connected to selected word line W6).
As to claim 12-13, Suk teaches wherein the control logic generates a second control signal for applying the program voltage to the select word line after the pass voltage increase period; wherein the switching circuits connect the program voltage regulator with the select word line in response to the second control signal. (As found in at least FIG. 6, in an obvious manner, control logic, having switching circuits, in FIGS. 2 and 21 apply program voltage Vpgm to selected word line after applying the pass voltage increase).
As to claim 14, Suk teaches wherein the switching circuits maintain a connection between the first pass voltage regulator and the unselect word lines and releases a connection between the second pass voltage regulator and the select word line (As found in at least FIG. 6, in an obvious manner, it is taught that first pass voltage Vpass1 is maintained on at least WL1, while Vpass2 is released from selected word line WL6).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 5712721852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827
Prosecution Insights