DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. Claims 1-20 are present for examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1-5, 8, 11-15 & 20 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al (US 2020/00279863).
Claims 1 & 12, Liu et al (see Fig. 7 below), & para [0057]), obviously shows a semiconductor device comprising a memory cell array (stacked/memory NAND chip 702), over a first substrate 708, including a vertical stack of memory cells (NAND type) and a vertical stack of pad portions; and forming a peripheral circuit region 740 (or peripheral chip 704 formed on a second substrate 720, see also para [0057-0061]), vertically overlapping the vertical stack of metal layers and/or vertical bonding pad/contact portions (730, 716, 732), which also couples to a horizontal array of dielectric & word line layers (embedded in the 712 layers) for this cell array 702, and plurality of contact plugs (730, 716, 732) disposed above and coupled to the pad portions; and a multi-layer level metal wiring (metal layers 712, 718) acting as the claimed word lines or sub-word lines, and a bonding structure 706 for bonding two different devices (memory/cell stack 702 and peripheral circuit/stacks 704 together), and also including first bonding pads 730 coupled to the contact plugs and second bonding pads 716 coupled to such multi-layer word lines.
It is noted that even though Liu does not specially mentions usage of “sub-word line or sub-word lines drivers”; however, such language is considered as well-known and inherent design features for any conventional cell array of today because any memory cell array, which commonly has a plurality of main word lines and plurality of main bit lines, but since due to its complexity and sizes, it can be divided further into a plurality of smaller/convenient cell blocks, and with each individual block also has respective sub-word lines and sub-bit lines as well. Thus, obviously each cell block from Liu teachings above could also have multiple sub-blocks having corresponding multiple sub-word line drivers and local bit lines (besides its main word line and main bit lines as well) arranged in similar fashion, and that this Liu cell array could also have its own main word line drivers as well as respective sub-word lines drivers and/or local sense amplifiers, if any, and all these features are already considered as conventional knowledge, which are also well-known to any skilled person in the memory art of today technology.
[AltContent: textbox (Sub-word metal lines/layers 112
arranged in parallel or horizontally)][AltContent: textbox (Memory NAND cell
array/chip 702 with first substrate 708)][AltContent: textbox (Peripheral chip 704 with second substrate 720)][AltContent: textbox (Main/wafer bonding interface 706 between two wafer chips for bonding two different chip structures)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (Vertical/stacked bonding pads
732, 730, 716, 718)][AltContent: arrow][AltContent: arrow][AltContent: textbox (Control circuit/layers for
sub-word lines drivers 740)]
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732
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Claims 2-3 & 13, Fig. 7 above also shows the word lines arranged in parallel, thus also suggests that their respective sub-word lines could have been horizontally disposed to each other similarly and coupled to respective driver circuitry (formed in the peripheral chip region 740) for driving each pad stacks below.
Claim 4-5 & 14-15, Fig. 17 shows the plurality of vertical/stacked bonding pads are also divided into different pad groupings, one group on left side for interfacing with the cell array, and one right side for bonding with the sub-word lines drivers for example. Additionally, these pad groups are obviously arranged along the horizontal direction as claimed.
Claims 8 & 20, Fig. 7 shows one embodiment wherein the cell array (chip 702) is disposed at a lower level than the peripheral circuit region 740, and the whole structure formed as a 3D cell structure over a first substrate 708 as claimed.
Claim 11, Fig. 7 shows the peripheral chip 704 and memory chip 702 are flipped such that their respective bonding pad/contacts (I.e., see 730 contact/pads from the memory chip 702 (below) and the 732 contact/pads from peripheral chip 704 (above) for example) could be wafer-bonded with each other as claimed.
Allowable Subject Matter
3. The following claims 6-7, 9-10, 16-19 are objected to being dependent upon the rejected claims above, but they also tentatively contain other/novel limitations to the recited structure above, which are all neither clearly suggested by the existing prior arts nor seen elsewhere at this time as follows:
- Claims 6-7 & 17-18 add novel limitations to the design of “stepping pad portions” disposed at horizontal ends, and the “common gate” of shared WL drivers;
- Claims 9-10 & 19 add novel usage of “vertical/stacked capacitors” and a “double structure of crossing the horizontal layer while overlapping the horizontal layer oriented from the bit lines”.
- Claim 16 adds a “vertical stack of capacitors horizontally neighboring the vertical stack of transistors”.
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIET Q NGUYEN whose telephone number is (571)272-1788. The examiner can normally be reached M-F 7:30-3PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VIET Q NGUYEN/Primary Examiner, Art Unit 2827
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