SINGLE ENDED SENSE AMPLIFIER WITH CURRENT PULSE CIRCUIT

Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION In response to the Communications dated January 23, 2025, claims 1-20 are active in this application. Specification If there are cross-reference to related applications, please include the respective patent numbers, if known. Information Disclosure Statement The information disclosure statements filed January 23, 2025, have been considered. Claim Objections Claims 19 and 20 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. Claims 1-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-9 of U.S. Patent No. 12243614 [‘614]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason. The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows. Present Application Patent ‘614 1. A memory circuit, comprising: a bit cell having a resistor configurable to a low resistive state and a high resistive state; a p-type metal-oxide semiconductor (PMOS) transistor having a drain connected to a data path of the bit cell; and a NAND gate having an output coupled to a gate of the PMOS transistor, wherein a first input of the NAND gate is controlled by a state of the bit cell; wherein a source of the PMOS transistor is connected to a current source, and wherein the current source increases an applied read current to the data path with an injected current pulse in response to detection of a low to high transition of a resistive state of the bit cell. 1. A memory circuit, comprising: a bit cell having a resistor configurable to a low resistive state and a high resistive state; a p-type metal-oxide semiconductor (PMOS) transistor having a drain connected to a data path of the bit cell; and a NAND gate having an output coupled to a gate of the PMOS device, wherein a first input of the NAND gate is controlled by a state of the bit cell; wherein the memory circuit is embodied in one of a resistive random access memory (RRAM) or a Magnetoresistive random-access memory (MRAM). 4. The memory circuit of claim 3, wherein a source of the PMOS transistor is connected to a current source, and wherein the current source increases an applied read current to the data path with an injected current pulse in response to detection of a low to high transition of a resistive state of the bit cell. 2. The memory circuit of claim 1, wherein the memory circuit is embodied in one of a resistive random-access memory (RRAM) or a Magnetoresistive random-access memory (MRAM). See claim 1 – “the memory circuit is embodied in one of a resistive random access memory (RRAM) or a Magnetoresistive random-access memory (MRAM).” 3. The memory circuit of claim 1, wherein a second input of the NAND gate is controlled by a pulse signal. 2. The memory circuit of claim 1, wherein a second input of the NAND gate is controlled by a pulse signal. 4. The memory circuit of claim 3, wherein the bit cell comprises a resistive sense memory cell. 3. The memory circuit of claim 2, wherein the bit cell comprises a resistive sense memory cell. 5. The memory circuit of claim 1, further comprising a sensing circuit having a reference resistor. 5. The memory circuit of claim 4, further comprising a sensing circuit having a reference resistor. 6. The memory circuit of claim 5, wherein the sensing circuit detects a voltage drop across the bit cell in response to an applied read current during a read operation and generates a high or low logic output at an output node of the sensing circuit. 6. The memory circuit of claim 5, wherein the sensing circuit detects a voltage drop across the bit cell in response to an applied read current during a read operation and generates a high or low logic output at an output node of the sensing circuit. 7. The memory circuit of claim 6, wherein the injected current pulse comprises an equalization start pulse and the resistive state of the bit cell comprises a previous output logic value from the output node. 7. The memory circuit of claim 6, wherein the pulse signal comprises an equalization start pulse and the state of the bit cell comprises a previous output logic value from the output node. 8. The memory circuit of claim 7, further comprising an equalization start circuit that generates the equalization start pulse from an equalization start signal, wherein the equalization start pulse is approximately 3 nanoseconds in duration and the equalization start signal is approximately 10 nanoseconds in duration. 8. The memory circuit of claim 7, further comprising an equalization start circuit that generates the equalization start pulse from an equalization start signal, wherein the equalization start pulse is approximately 3 nanoseconds in duration and the equalization start signal is approximately 10 nanoseconds in duration. 9. The memory circuit of claim 6, wherein the read operation includes: a pre-equalization phase during which the sensing circuit is in an off state; an equalization phase during which the injected current pulse is selectively injected to the data path of the bit cell based on a previous output at the output node and the applied read current is provided to the bit cell and a reference resistor; and an execution phase during which a voltage drop across the bit cell is compared to a voltage drop across the reference resistor to determine a present logic output at the output node. 9. The memory circuit of claim 6, wherein the read operation includes: a pre-equalization phase during which the sensing circuit is in an off state; an equalization phase during which the current pulse is selectively injected to the data path of the bit cell based on a previous output at the output node and the applied read current is provided to the bit cell and a reference resistor; and an execution phase during which a voltage drop across the bit cell is compared to a voltage drop across the reference resistor to determine a present logic output at the output node. As can be seen from the above table, claim 1 of the present application is nearly identical to claim 1 of patent ‘614, with one critical structural difference: Identical Elements: Both claims require a memory circuit with a configurable resistor bit cell, a PMOS transistor connected to the data path, a NAND gate controlling the PMOS gate based on the bit cell state, and a current source that injects a current pulse upon detecting a low-to-high transition. The Difference: Patent ‘614 contains a species limitation: “wherein the memory circuit is embodied in one of a resistive random access memory (RRAM) or a Magnetoresistive random-access memory (MRAM)”. Claim 1 of the application omits this clause, claiming the memory circuit generically (a genus claim). Configuring a generic memory circuit with the identical electrical components and feedback logic described in patent ‘614 is an obvious generalization of the species disclosed in patent ‘614. It would have been obvious to one of ordinary skill in the art to apply the taught current-pulsing configuration to a general memory layout, as the core inventive concept—the logic and current-injection feedback loop—remains completely unchanged. Therefore, coverage have already been given to the earlier filed patent application. For similar reasons, claims 2-9 are rejected over claims 1-9 of patent ‘614. Claims 10-13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 10-13 of U.S. Patent No. 12243614 [‘614]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason. The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows. Present Application Patent ‘614 10. A sense amplifier, comprising: a bit cell coupled to a sensing circuit via a data path wherein the bit cell includes a resistor configurable to a low resistive state and a high resistive state; a transistor coupled between a current source and the data path; and a NAND gate having an output coupled to a gate of the transistor, wherein a first input of the NAND gate is controlled by an output node of the sensing circuit. 10. A sense amplifier, comprising: a bit cell coupled to a sensing circuit via a data path, wherein the bit cell includes a resistor configurable to a low resistive state and a high resistive state; a p-type metal-oxide semiconductor (PMOS) transistor having a drain connected to the data path; and a NAND gate having an output coupled to a gate of the PMOS transistor, wherein a first input of the NAND gate is controlled by an output node of the sensing circuit. 11. The sense amplifier of claim 10, wherein the sense amplifier is embodied in one of a resistive random-access memory (RRAM) or a Magnetoresistive random-access memory (MRAM). 11. The sense amplifier of claim 10, wherein the sense amplifier is embodied in one of a resistive random-access memory (RRAM) or a Magnetoresistive random-access memory (MRAM). 12. The sense amplifier of claim 10, wherein a second input of the NAND gate is controlled by a pulse signal. 12. The sense amplifier of claim 10, wherein a second input of the NAND gate is controlled by a pulse signal. 13. The sense amplifier of claim 12, wherein the pulse signal comprises an equalization start pulse and a state of the bit cell comprises a previous output logic value from the output node. 13. The sense amplifier of claim 12, wherein the pulse signal comprises an equalization start pulse and a state of the bit cell comprises a previous output logic value from the output node. As can be seen from the above table, claim 10 of the present application is nearly identical to claim 10 of patent ‘614: Both have identical core architecture - Sense amplifier with a bit cell, sensing circuit, data path, configurable resistor, and a NAND gate. Both have identical control logic - NAND gate output coupled to the gate of the transistor; first input controlled by the sensing circuit output. They differ in that, claim 10 of the application broadens the PMOS, of claim 10 of patent ‘614, to any transistor. Additionally, PMOS transistors inherently source current when configured this way; adding "current source" is an obvious functional description of a PMOS pull-up setup. Claim 10 of Patent ‘614 claims a specific species (PMOS transistor), while claim 10 of the application claims the genus (transistor). Claiming a broader genus does not define a patentably distinct invention. Additionally, a PMOS transistor with its drain on a data path typically has its source connected to a power supply (V_DD), acting as a switched current source. The application describing it as "coupled between a current source and the data path" is a structural and functional equivalent that would be completely obvious to a person having ordinary skill in the art. Therefore, coverage has already been given to the earlier filed patent application. For similar reasons, claims 11-13 are rejected over claims 11-13 of patent ‘614. Claims 14-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 5, 6 and 8 of U.S. Patent No. 12243614 [‘614]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason. The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows. Present Application Patent ‘614 14. A sense amplifier, comprising: a bit cell coupled to a sensing circuit via a data path wherein the bit cell includes a resistor configurable to a low resistive state and a high resistive state; a transistor coupled between a current source and the data path; and a pulse generation circuit coupled to a gate of the transistor that causes a pulse current to be injected on the data path during low to high resistive state transitions of the bit cell. 1. A memory circuit, comprising: a bit cell having a resistor configurable to a low resistive state and a high resistive state; a p-type metal-oxide semiconductor (PMOS) transistor having a drain connected to a data path of the bit cell; and a NAND gate having an output coupled to a gate of the PMOS device, wherein a first input of the NAND gate is controlled by a state of the bit cell; wherein the memory circuit is embodied in one of a resistive random access memory (RRAM) or a Magnetoresistive random-access memory (MRAM). 4. The memory circuit of claim 3, wherein a source of the PMOS transistor is connected to a current source, and wherein the current source increases an applied read current to the data path with an injected current pulse in response to detection of a low to high transition of a resistive state of the bit cell. 15. The sense amplifier of claim 14, wherein the pulse generation circuit includes a NAND gate having an output coupled to a gate of the transistor, a first input coupled to an equalization start circuit, and a second input coupled to an output of the sense amplifier. 6. The memory circuit of claim 5, wherein the sensing circuit detects a voltage drop across the bit cell in response to an applied read current during a read operation and generates a high or low logic output at an output node of the sensing circuit. 16. The sense amplifier of claim 15, wherein the equalization start circuit generates a equalization start pulse of approximately 3 nanoseconds in duration from an equalization start signal of approximately 10 nanoseconds in duration. 8. The memory circuit of claim 7, further comprising an equalization start circuit that generates the equalization start pulse from an equalization start signal, wherein the equalization start pulse is approximately 3 nanoseconds in duration and the equalization start signal is approximately 10 nanoseconds in duration. 17. The sense amplifier of claim 14, wherein the transistor comprises a p-type metal- oxide semiconductor (PMOS) transistor having a drain connected to the data path. See claim 1 – “a p-type metal-oxide semiconductor (PMOS) transistor having a drain connected to a data path of the bit cell; and a NAND gate having an output coupled to a gate of the PMOS device”. 18. The sense amplifier of claim 14, further comprising a sensing circuit having a reference resistor. 5. The memory circuit of claim 4, further comprising a sensing circuit having a reference resistor. As can be seen from the above table, claim 14 of the present application is nearly identical to claim 1 of patent ‘614: Both have identical core architecture - Sense amplifier with a bit cell, sensing circuit, and data path. Both have identical control logic - Configurable to low/high resistive states. Claim 1 of the patent ‘614 claims a specific species (a PMOS transistor and a NAND gate logic structure). Claim 14 of the application claims a broader genus (a generic transistor and a pulse generation circuit performing the operational equivalent of injecting a transition pulse). Because claim 14 of the application merely broadens the exact hardware implementation explicitly stated in claim 1 of the patent ‘614, the variations are likely patentably indistinct. Therefore, coverage has already been given to the earlier filed patent application. For similar reasons, claims 15-18 are rejected over claims 1, 5, 6 and 8 of patent ‘614. Allowable Subject Matter The following is an Examiner's statement of reasons for the indication of allowable subject matter: the prior art of records does not show (in addition to the other elements in the claim) the following: -with respect to claim 19: The sense amplifier of claim 18, further comprising a latch for storing a sensed data voltage drop across the reference resistor. Conclusion For applicant’s benefit portions of the cited reference(s) have been cited to aid in the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI. When responding to the Office action, Applicants are advised to provide the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case. Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M. Any inquiry of a general nature or relating to the status of this application. should be directed to the Group receptionist whose telephone number is (571) 272-1650. /MICHAEL T TRAN/Primary Examiner, Art Unit 2827 October 13, 2026