DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the plurality o" in line 10 of page 25. There is insufficient antecedent basis for this limitation in the claim.
Claim 1 recites the limitation "the word line driver circuits" (plural circuits) in line 11 of page 25. There is insufficient antecedent basis for this limitation in the claim.
Claim 1 recites the limitation "the word lines" in line 11 of page 25. There is insufficient antecedent basis for this limitation in the claim.
Claim 1 recites the limitation "the given bit line" in line 21 of page 25. There is insufficient antecedent basis for this limitation in the claim.
Claims 2-10 are rejected because they depend on claim 1; and therefore, contain at least the same defect(s).
Claim 11 recites the limitation "the plurality o" in line 8 of page 28. There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation "the word line driver circuits" (plural circuits) in line 9 of page 28. There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation "the word lines" in line 9 of page 28. There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation "the given bit line" in line. There is insufficient antecedent basis for this limitation in the claim.
Claims 12-19 are rejected because they depend on claim 1; and therefore, contain at least the same defect(s).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2, 4, 10, 18, and 27 of U.S. Patent No. 12,237,007. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 2, 10, 18, and 27 of U.S. Patent No. 12,237,007 each express the limitations found in claim 1 of the instant application, where they are not explicitly recited.
That is, claims 2, 4, 10, 18, and 27 of U.S. Patent No. 12,237,007 each recite the limitations of claim 1 of the instant application except, “a bit line clamping circuit comprising: . . . a logic circuit having an input configured to receive the analog voltage on the given bit line and to generate a trigger signal in response to a comparison of the analog voltage to a threshold voltage of the logic circuit; wherein the trigger signal is used to control actuation of the first transistor to clamp the at least one bit line.”
However, claims 2, 4, 10, 18, and 27 of U.S. Patent No. 12,237,007 each recite, “a bit line clamping circuit comprising a sensing circuit configured to compare the analog voltage on a given bit line to a threshold voltage and a voltage clamp circuit that is actuated in response to the comparison to preclude the analog voltage on that given bit line from decreasing below a clamping voltage level.” Therein, under the broadest reasonable interpretation of claim 1 of the instant application, “a sensing circuit” of U.S. Patent No. 12,237,007 is interpreted to map to “a logic circuit,” and “a voltage clamp circuit that is actuated in response to the comparison to preclude the analog voltage on that given bit line from decreasing below a clamping voltage level” is interpreted to express the limitation, “the trigger signal is used to control actuation of the first transistor to clamp the at least one bit line.”
Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 6 and 37, in view of claims 2 and 27, respectively, of U.S. Patent No. 12,237,007. Although the claims at issue are not identical, they are not patentably distinct from each other because of reasons set forth in the NSDP rejection of claim 1 above and the Schmitt trigger circuit recited in claims 6 and 37.
Claim 3 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 7 and 38, in view of claims 2 and 27, respectively, of U.S. Patent No. 12,237,007. Although the claims at issue are not identical, they are not patentably distinct from each other because of reasons set forth in the NSDP rejection of claim 1 above and "logic circuit" of U.S. Patent No. 12,237,007 is interpretted to map to "a logic gate," and wherein, “an output of the sensing circuit” maps to “the trigger signal”.
Claim 4 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 4, 10, 18, and 28 of U.S. Patent No. 12,237,007. Although the claims at issue are not identical, they are not patentably distinct from each other because of reasons set forth in the NSDP rejection of claim 1 above and claims 4, 10, 18, and 28 of U.S. Patent No. 12,237,007 recite "a second transistor" (claim 28: "a fourth transistor") with the same configuration of the "second transistor" recited in claim 4, receiving a control signal.
Claim 5 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 10 and 29 of U.S. Patent No. 12,237,007. Although the claims at issue are not identical, they are not patentably distinct from each other because of reasons set forth in the NSDP rejection of claim 4 above and claims 10 and 29 recite "the control signal is an analog bias voltage" that determines the clamping voltage level.
Claim 6 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 11 and 30 of U.S. Patent No. 12,237,007. Although the claims at issue are not identical, they are not patentably distinct from each other because of reasons set forth in the NSDP rejection of claim 5 above and claims 11 and 30 recite "a voltage generating circuit configured to generate the analog bias voltage in response to a setting signal".
Claim 7 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 12 and 31 of U.S. Patent No. 12,237,007. Although the claims at issue are not identical, they are not patentably distinct from each other because of reasons set forth in the NSDP rejection of claim 5 above and claims 12 and 31 recite, "the setting signal is configured to cause modulation of the analog bias voltage away from a nominal level in response to an applicable integrated circuit process corner for transistor devices of the SRAM cells."
Claims 8 and 9 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 14 and 33 of U.S. Patent No. 12,237,007. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 14 and 33 recite, "the setting signal is configured to cause a temperature dependent tuning of the analog bias voltage in response to applicable integrated circuit process corner."
Claim 10 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9 and 39 of U.S. Patent No. 12,237,007. Although the claims at issue are not identical, they are not patentably distinct from each other because of reasons set forth in the NSDP rejection of claim 1 above and claims 9 and 39 recite, "the bit line clamping circuit is a component of a bit line precharge circuit."
Allowable Subject Matter
Claims 11-19 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUSTIN BRYCE HEISTERKAMP whose telephone number is (703)756-1095. The examiner can normally be reached M-F 0800-1700.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUSTIN BRYCE HEISTERKAMP/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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