Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are present for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Chanemougame et al. (US 20220102362 A1) in view of Cernea (US 20050024946 A1).
Regarding claim 1: Chanemougame discloses a static random access memory (SRAM) structure stack with memory circuits (FIG. 4A), comprising: memory cells (bit cell, FIG. 2), respectively comprising an inverter (INV1, FIG. 2) and two pass-gate transistors (PG1 and PG2, FIG. 2) coupled to two data nodes of the inverter (FIG. 2); pairs of bit lines (BL and !BL, FIG. 2), passing through the memory cells from above the memory cells (bit lines above, FIG. 4C), and coupled to the data nodes through the pass-gate transistors (bit lines coupled to pass gates, FIG. 2); and a power distribution network (buried power rails BPR, par. 50-51), powering the memory cells from below the memory cells (buried power rail VVS1, VSS2, VDD below bit cell, FIG. 4A-4C).
Chanemougane does not disclose each memory cell is intersected with a single one of the bit lines, and connected to the intersected one of the bit lines as well as another one of the bit lines passing through an adjacent one of the memory cells.
Cernea does disclose a memory system utilizing dual memory element format, comprising: wherein each memory cell is intersected with a single one of the bit lines (memory cell C1 connected to single bit line BL1, FIG 2), and connected to the intersected one of the bit lines as well as another one of the bit lines passing through an adjacent one of the memory cells (memory cell C1 connected to memory cell C2, through a select gate S1, C2 connected to single bit line BL2, FIG 2).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Chanemougane with the configuration of Cernea to allow the system to have a similar bit line sharing setup as the claimed invention.
Regarding claim 8: Chanemougame discloses a static random access memory (SRAM) structure stack with memory circuits (FIG. 4A), wherein the pass-gate transistors are controlled by word lines (word line WL connected to PG1 and PG2, FIG. 2) running above all of the bit lines (word lines WL can be positioned above bit lines BL, FIG. 4A and 4C).
Claim(s) 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 20160078922 A1) in view of Thyagarajan (US 20220293522 A1).
Regarding claims 9 and 20: Liaw discloses an SRAM cell setup (FIG. 12) comprising: a first memory cell and a second memory cell next to each other (dashed lines around SRAM cell, e.g., top-right most memory cell and adjacent top-left most memory cell, par. 32, FIG. 12) wherein each of the first and second memory cells respectively comprises: a first active structure (active region 22B, FIG. 9 and 12) and a second active structure (active region 22A, FIG. 9 and 12), respectively extending along and overlapping one of the power rails (FIG. 9 and 12); and a first gate structure, a second gate structure, a third gate structure and a fourth gate structure (horizontal structures, unmarked, across nodes PG-1, PD-1, PU-1, PG-2, PD-2, and PU-2, FIG. 9 and 12), covering and intersecting each of the first and second active structures (gate structures overlap 22A and 22B, FIG. 9 and 12), wherein N-type transistors (N-type MOS transistors, par. 19, FIG. 1) comprising a first pass-gate transistor (PG-1), a first pull-down transistor (PD-1), a second pull-down transistor (PD-2) and a second pass-gate transistor (PG-2) are defined at intersections of the first active structure and the first to fourth gate structures (intersections of 22B and unmarked horizontal gate structures, FIG. 9 and 12), P-type transistors (P-type MOS transistors, par. 19, FIG. 1) comprising a first pull-up transistor (PU-1) and a second pull-up transistor (PU-2) are defined at intersections of the second active structure and the first to fourth gate structures respectively (intersections of 22A and unmarked horizontal gate structures, FIG. 9 and 12);, the first and second pull-down transistors are connected to the power rail overlapped with the first active structure by a common source/drain terminal (PD-1 and PD-2 connected to power rail Vdd 15-4 overlapping 22B, FIG. 12), and the first and second pull-up transistors are connected to the power rail overlapped with the second active structure by a common source/drain terminal (PU-1 and PU-2 connected to power rail Vss 15-3 overlapping 22A, FIG. 12); and bit lines (bit-line BL and BLB, 15-1 and 15-2, and 52-1 and 52-2, FIG. 9 and 12), lying over and crossing the memory cells (FIG. 9 and 12), wherein the first pass-gate transistor in the first memory cell is connected to a first bit line (PG-1 connected to 15-2/52-2, top-right most memory cell, FIG. 12) of the bit lines which intersects the first memory cell (dashed lines around SRAM cell, top-right most memory cell, par. 32, FIG. 12), and the second pass-gate transistor in the first memory cell is connected to a second bit line (PG-2 of horizontally adjacent SRAM cell connected to 15-1/52-1, top-left most memory cell, FIG. 12) of the bit lines which intersects the second memory cell (top-left most memory cell, FIG. 12).
Liaw does not disclose a power distribution network powering the memory cells from below the memory cells. comprising layers of power rails.
Thyagarajan does disclose a buried power rail architecture for SRAM instances (par. 14, FIG. 1-2) comprising: a power distribution network (backside buried power rails network architecture 100, FIG. 1-2) powering the memory cells from below the memory cells (buried power rails disposed underneath the memory cells of SRAM memory instance 108, FIG. 1), comprising layers of power rails (backside buried power rails over a plurality of layers e.g., BM0, BM1, BM2 under memory instance 108, par. 12, FIG. 1).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Liaw with the power rail configuration of Thyagarajan to allow the system to have the multi-layered backside power network as the claimed invention.
Allowable Subject Matter
Claims 2-7, and 10-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject
matter:
Claims include allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: a common source/drain terminal of the first and second pull-down transistors in each memory cell is bridged to a common source/drain terminal of the first and second pull-down transistors in an adjacent one of the memory cells through a first lateral contact, and a common source/drain terminal of the first and second pull-up transistors in each memory cell is bridged to a common source/drain terminal of the first and second pull-up transistors in an adjacent one of the memory cells through a second lateral contact as in claim 2; wherein the memory cells are connected to the bit lines through third lateral contacts in between, and the third lateral contacts each extend through an interface shared by two adjacent ones of the memory cells as in claim 6; wherein the first pass-gate transistor in the first memory cell is connected to the first bit line via a first lateral contact, and the second pass- gate transistor in the first memory cell is connected to the second bit line through a second lateral contact as in claim 10; and wherein a common source/drain terminal of the first pass-gate transistor and the first pull-down transistor as well as a source/drain terminal of the first pull-up transistor in each memory cell are connected through a third lateral contact, and a common source/drain terminal of the second pass-gate transistor and the second pull-down transistor as well as a source/drain terminal of the second pull-up transistor in each memory cell are connected through a fourth lateral contact as in claim 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY THINH TANG/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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