DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Note that citations to figures and elements should be understood to also implicitly refer to any pertinent explanatory text in the reference.
Claims 1, 7-11 are rejected under 35 U.S.C. 103 as being unpatentable in view of different teachings of US 2022/0375398 A1 (Liao).
Regarding claim 1, Liao teaches a driving structure for a display panel (Abstract), comprising:
a controller (Fig. 2 at 30 and/or 36), disposed on the display panel (Fig. 2 at 10), generating a data signal ([16]) and a timing signal ([16]);
at least one driver (Fig. 2 at 22), disposed on the display panel (Fig. 2 at 10), receiving the data signal (Fig. 3 at Din) and the display clock signal (Fig. 3 at PWMCLK); and
a data detection circuit (Fig. 3 at 26), detecting a content of the data signal ([17], [20]: the storage circuit detects content of the data signal in storing input data and also in sending pixel data to driving circuit).
Liao does not expressly teach that the controller transmits the display clock signal, but the suggestion to do so is present as Liao teaches that the controller transmits a timing signal ([16]) and Liao teaches that the driver receives a display clock signal (Fig. 3 at PWMCLK). The motivation is to provide the display clock signal. The combination would have been unsurprising and had a reasonable expectation of success because a display clock signal is a form of timing signal. Thus, before the effective filing date of the current application, the combination of teachings of Liao would have rendered obvious, to one of ordinary skill in the art, that the controller generates a display clock signal.
Regarding claim 7, Liao teaches wherein the controller generates an enable signal and transmits the enable signal to the at least one driver, and the at least one driver starts to receive the data signal and the display clock signal according to the enable signal ([18], [22]).
Regarding claim 8, Liao teaches wherein the at least one driver comprises a first driver and a second driver, the first driver is coupled to the second driver in series, and the first driver transmits another enable signal to the second driver after the first driver receiving the enable signal ([18]-[19]; Fig. 2).
Regarding claim 9, Liao does not expressly teach that the controller transmits a data clock signal, but the suggestion to do so is present as Liao teaches that the controller transmits a timing signal ([16]) and Liao teaches that the driver receives a data clock signal (Fig. 3 at DCLK). The motivation is to provide the data clock signal. The combination would have been unsurprising and had a reasonable expectation of success because a display clock signal is a form of timing signal. Thus, before the effective filing date of the current application, the combination of teachings of Liao would have rendered obvious, to one of ordinary skill in the art, wherein the controller generates a data clock signal and transmits it to the at least one driver. Liao further teaches that the at least one driver receives the data signal according to the data clock signal (Fig. 3 at Din, DCLK).
Regarding claim 10, Liao teaches wherein the at least one driver comprises a first driver and a second driver (Fig. 2 at 22), the first driver is coupled to the second driver in series (Fig. 2 at 22), and both the first and second drivers receive the data clock signal (Fig. 3 at DCLK). Liao does not expressly teach that the first and second drivers simultaneously receive the data clock signal. There is the problem of when to supply the data clock signal to the drivers. There are two possibilities, simultaneously or not simultaneously. It would have been obvious to one of ordinary skill in the art to try simultaneously. Furthermore, simultaneous reception of the data clock signal would have been suggested and motivated for one of ordinary skill in the art as clock signals should be synchronized with each other in order for the various parts of the device to operate on proper time. Thus, before the effective filing date of the current application, Liao and obviousness to try would have rendered obvious, to one of ordinary skill in the art, that the first and second drivers simultaneously receive the data clock signal.
Regarding claim 11, Liao teaches wherein the at least one driver comprises:
a data receiver/detector (Fig. 3 at 26), detecting the content of the data signal and allocating the data signal ([17], [20]: the storage circuit detects and allocates content of the data signal in storing input data and also in sending pixel data to driving circuit);
a memory circuit, storing the data signal (Fig. 3 at 261 and/or 265);
a counter, generating a counting signal according to the display clock signal (Fig. 3 at 283);
a comparator, receiving the data signal and the counting signal and generating a comparison result (Fig. 3 at 281); and
a current source circuit, driving a light emitting component according to the comparison result ([24]; Fig. 3 at VDD, 14, 286, 288).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0375398 A1 (Liao) as applied to claim 1 above, and further in view of US 2024/0152196 A1 (Garcia).
Regarding claim 6, Liao teaches wherein the data detection circuit is disposed in the at least one driver ([17], [20]), but does not expressly teach wherein the data detection circuit is disposed in both the controller and the at least one driver. Garcia teaches wherein a data detection circuit is disposed in the controller ([35]). The suggestion to modify the teaching of Liao by the teaching of Garcia is present as both teach displays. The motivation is to implement different power saving modes. The data detection elements taught by Liao and the data detection elements taught by Garcia may be considered part of one data detection circuit. Therefore, in view of the teachings of Liao and Garcia, it would have been obvious to one of ordinary skill in the art, wherein the data detection circuit is disposed in both the controller and the at least one driver. Alternatively, it is generally considered obvious to make elements separable. MPEP 2144(V)(C). It is generally considered obvious to rearrange parts. MPEP 2144(VI)(C). These techniques are particularly applicable to electronics. Therefore, in view of the teachings of Liao and Garcia as well as the obviousness of making elements separable and rearrangement of parts, it would have been obvious to one of ordinary skill in the art, wherein the data detection circuit is disposed in both the controller and the at least one driver.
Allowable Subject Matter
Claims 2-5 and 12-14 are subject to objection as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter.
Claims 2-5 and 12-14, subject to objection as being dependent upon a rejected claim, would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if any formal objections are successfully addressed, because the prior art cited to reject the aforementioned base and intervening claims does not subsequently teach or render obvious the dependent claims indicated as otherwise allowable in the full context of the claims. Nor does any observed additional prior art in combination with the cited prior art render obvious the dependent claims indicated as being allowable in the full context of the claims.
Response to Arguments
Applicant's arguments filed 02 April 2026 regarding claim 1 have been fully considered but they are not persuasive.
Applicant argues that Liao does not teach a data detection circuit detecting a content of the data signal. Remarks at 8-10. However, Liao teaches that the storage circuit stores input data and from the input data sends pixel data to the driving circuit ([17], [20]). Thus, the limitation “detecting a content of the data signal” is broad enough to read onto the teaching of Liao, as either or both of the actions of storing input data and determining whether stored received input data is pixel data to be sent may be considered to read onto the limitation “detecting a content of the data signal”.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GENE W LEE whose telephone number is (571)270-7148. The examiner can normally be reached M-F 9:30am-6:00pm.
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/Gene W Lee/Primary Examiner, Art Unit 2624
Prosecution Insights