Prosecution Insights
Last updated: October 04, 2026
Application No. 19/036,100

Driving structure for display panel

Final Rejection §102
Filed
Jan 24, 2025
Priority
Jan 25, 2024 — provisional 63/624,807
Examiner
MATTHEWS, ANDRE L
Art Unit
2621
Tech Center
2600 — Communications
Assignee
Sitronix Technology Corporation
OA Round
2 (Final)
62%
Grant Probability
Moderate
3-4
OA Rounds
1y 9m
Est. Remaining
77%
With Interview

Examiner Intelligence

Grants 62% of resolved cases
62%
Career Allowance Rate
329 granted / 529 resolved
At TC average
Moderate +14% lift
Without
With
+14.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
14 currently pending
Career history
554
Total Applications
across all art units

Statute-Specific Performance

§101
1.9%
-38.1% vs TC avg
§103
70.9%
+30.9% vs TC avg
§102
12.1%
-27.9% vs TC avg
§112
13.4%
-26.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 529 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liao (US 2022/0375398). Regarding claim 1, Liao teaches A driving structure for a display panel, comprising: a controller, disposed on the display panel ( Fig. 1 control circuit 30), generating a data signal and a data clock signal ([0013]) ; and at least one driver, disposed on the display panel (Fig. 1 drivers 22), receiving the data signal and the data clock signal (Fig. 3 shows storage circuit 26 of driver 22 receiving data signal Din and data clock signal DClk), wherein the controller sets a signal level (enable) of the data clock signal according to whether the at least one driver needs to update data thereof (timing controller 36 of controller 30 transmits the input data to the driving group 22and generates timing signals according to control parameters [0016]. Fig. 2 also shows the timing controller transmits the enable signal to the enable circuit 24 of the driving groups 22[0017-0019]). Regarding claim 2, Liao teaches wherein the at least one driver receives the data signal according to a timing of the data clock signal ([0013] teaches the drivers 22 will receive input data at different times, when a driver 22 of the driving group 20 receives the input data, the other drivers 22 do not receive the input data. After this driver 22 receives the pixel data of the input data, another driver 22 is driven by this driver 22 to receive the input data for receiving another pixel data of the input data.). Regarding claim 3, Liao teaches wherein the controller sets a signal level of the data signal and the signal level of the data clock signal according to whether the at least one driver needs to update the data thereof (([0013] teaches the drivers 22 will receive input data at different times, when a driver 22 of the driving group 20 receives the input data, the other drivers 22 do not receive the input data. After this driver 22 receives the pixel data of the input data, another driver 22 is driven by this driver 22 to receive the input data for receiving another pixel data of the input data. Therefore its clear the data clock signal will start the transmission of data to the driver in a time-divisionally manner [0022]). Regarding claims 4, Liao teaches wherein the at least one driver comprises a first driver and a second driver, the controller transmits a first enable signal to the first driver, the first driver transmits a second enable signal to the second driver according to the data signal and the data clock signal ([0013][0018-0019]). Regarding claim 5, Liao teaches wherein the first driver starts to receive the data signal and the data clock signal according to the first enable signal, and the second driver starts to receive the data signal and the data clock signal according to the second enable signal ([0013][0018-0019] teach that when the first driver is enable to receive the other drivers are disabled until the first driver is finished then the clock signal is passed to the next driver to be enable while the other drivers are disabled.). Allowable Subject Matter Claims 6-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claim 6 is indicated allowable because the at least one driver transmits an enable signal according to a level variation of the first data signal, in combination with the other claim limitations.. Claim 8 is indicated allowable because the at least one driver transmits an enable signal according to a level variation of the second data signa, in combination with the other claim limitations. Claim 10 is indicated allowable because at least one driver transmits an enable signal according to level variations of the first and second data signals, in combination with the other claim limitations. Response to Arguments Applicant's arguments filed 4/21/2025 have been fully considered but they are not persuasive. In the remarks submitted the Applicant has argued Liao fails to teach the limitations of claim 1.Specifically the Applicant has argued Liao fails to teach “the controller sets a signal level of the data clock signal according to whether the at least one driver needs to be updated thereof” because Liao teaches an enable signal generated to enable circuit 24 not to update clock signal of the storage circuit 26. The Examiner respectfully disagrees. In [0016] Liao teaches the input interface 32 transmits the input data to the buffer 34. The buffer 34 buffers the input data and transmits the buffered input data to the timing controller 36. The timing controller 36 transmits the input data to the driving group 22 via the bus and outputs a timing signal to the driver 22 of the driving group 22 for controlling the operation of the driver 22. In [0017] Liao teaches The storage circuit 26 is coupled to the timing controller 36 of the control circuit 30 via the bus for receiving the input data transmitted by the timing controller 36. The enable circuit 24 is coupled to the storage circuit 26 and enables the storage circuit 26 for driving the storage circuit 26 to receive and store the input data. Since it is well known that transmitting data signals to a driver from a timing controller is done for a set period of time then it becomes understood that the data signal transmitted from the timing controller 36 to a driver 22 is done using a start time for transmission and an end time for transmission. In [0026] of the Applicant’s publication it is disclosed that when the enable signal is transmitted to the driver that needs to be updated a data clock signal (DCK) is set as the timing signal to set the data signals to the data transmission state. That is the data clock signal (DCK) is used to set a start time and end time for the data signal transmission. Although Liao does not explicitly teach a data clock signal he does teach the data signals are transmitted for a period of time based on a start time for transmission and an end time for transmission and therefore it is understood that Liao meets the limitations of the claim language. In regards to Liao sending the data clock signal to at least one driver that needs to update data thereof. Since it is well known to those skilled in the art that as image changes the input data of the pixels change which results in updating a data/source driver for the pixel images. Therefore if a plurality of data drivers are used to display an image then it is reasonable that a driver needed to change the pixel image is a driver needed to be updated, and a display system as taught by Liao would provided the data signals and timing parameters to the driver to produce the desired image as taught by Liao in [0013][0019]. With respect to the arguments submitted by Applicant on pages 4-5, In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., [0004 of applicant’s application) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRE L MATTHEWS whose telephone number is (571)270-5806. The examiner can normally be reached Mon-Fri 9:00-6:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached at 571-272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANDRE L MATTHEWS/ Primary Examiner, Art Unit 2621
Read full office action

Prosecution Timeline

Jan 24, 2025
Application Filed
Dec 22, 2025
Non-Final Rejection mailed — §102
May 21, 2026
Response Filed
Aug 13, 2026
Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12711889
CONTROL OF THE IMAGE REPRODUCTION OF A DISPLAY APPARATUS
4y 4m to grant Granted Aug 18, 2026
Patent 12710863
DISPLAY CONTROL APPARATUS, DISPLAY CONTROL METHOD, AND DISPLAY CONTROL PROGRAM
1y 5m to grant Granted Aug 18, 2026
Patent 12699497
VIRTUAL USER INPUT CONTROLS IN A MIXED REALITY ENVIRONMENT
1y 8m to grant Granted Aug 04, 2026
Patent 12693824
DISPLAY METHOD, CHIP, AND ELECTRONIC DEVICE
2y 5m to grant Granted Jul 28, 2026
Patent 12688804
TEST SYSTEM, METHOD OF TESTING DISPLAY CELL USING THE SAME, AND DISPLAY DEVICE
3y 7m to grant Granted Jul 21, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
62%
Grant Probability
77%
With Interview (+14.5%)
3y 5m (~1y 9m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 529 resolved cases by this examiner. Grant probability derived from career allowance rate.

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