Prosecution Insights
Last updated: September 17, 2026
Application No. 19/036,193

Voltage detection circuit and voltage detection system

Non-Final OA §102§103
Filed
Jan 24, 2025
Priority
Jan 26, 2024 — provisional 63/625,303
Examiner
PATEL, DHARTI HARIDAS
Art Unit
Tech Center
Assignee
Infsitronix Technology Corporation
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
1106 granted / 1266 resolved
+27.4% vs TC avg
Moderate +8% lift
Without
With
+7.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
20 currently pending
Career history
1276
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
42.8%
+2.8% vs TC avg
§102
44.0%
+4.0% vs TC avg
§112
2.4%
-37.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1266 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 2, 6, and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bruce et al. Publication No. US 2008/0239603. Regarding claims 1 and 10, Bruce discloses a voltage detection circuit, comprising: a control terminal [Fig. 3, gate terminal of the transistor 310], comprising a control terminal voltage [gate voltage]; a load terminal [Fig. 3, output terminal at 308], comprising a load terminal voltage; and a voltage detection unit [Fig. 3, operation amplifier 320], coupled to the control terminal and the load terminal, converting the control terminal voltage to a low-level voltage according to a voltage between the control terminal voltage and the load terminal voltage [par. 0049]. Regarding claim 2, Bruce discloses that a detection voltage is between the control terminal voltage and the load terminal voltage, the voltage detection unit sets a threshold voltage, and when the detection voltage exceeds the threshold voltage, the voltage detection unit converts the control terminal voltage to the low level voltage [Par. 0049 describes that Fig.3 operates by detecting a voltage that crosses a zero or positive directional threshold between the source and drain; a positive voltage from the source to the drain triggers the operational amplifier to shut off the transistor]. Regarding claim 6, Bruce discloses that the voltage detection unit comprises a comparator [Fig. 3, 320], the comparator is coupled to the control terminal [Fig. 3, gate terminal G of the transistor 310] and the load terminal [Fig. 3, the load terminal 306 connected to the (+) terminal of 320], and the comparator compares the control terminal voltage with the load terminal voltage and outputs a comparison result [Fig. 3, output of the operation amplifier 3200]. Regarding claim 9, Bruce further comprises a power startup unit [par. 0003; battery packs], wherein the power startup unit is coupled to the voltage detection unit, and outputs a start signal to the voltage detection unit [as shown in Fig. 3]. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 3-4 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Bruce et al. Publication No. US 2008/0239603. Regarding claims 3 and 4, Bruce discloses that the detection voltage exceeds a threshold voltage. However, Bruce does not disclose that when the detection voltage exceeds a multiple of the threshold voltage, the voltage detection unit converts the control terminal voltage to the low level voltage. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have the detection voltage exceed a multiple of the threshold voltage, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980). Regarding claims 11 and 12, Bruce discloses that a detection voltage is between the control terminal voltage and the load terminal voltage, the voltage detection unit sets a threshold voltage, and when the detection voltage exceeds the threshold voltage, the voltage detection unit converts the control terminal voltage to the low level voltage [Par. 0049 describes that Fig.3 operates by detecting a voltage that crosses a zero or positive directional threshold between the source and drain; a positive voltage from the source to the drain triggers the operational amplifier to shut off the transistor]. However, Bruce does not disclose that when the detection voltage exceeds a multiple of the threshold voltage (1.1 to 1.5 times the threshold voltage), the voltage detection unit converts the control terminal voltage to the low level voltage. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have the detection voltage exceed a multiple of the threshold voltage, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980). Allowable Subject Matter Claims 5 and 7-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for allowance of claim 5: The prior art does not further comprise a setting terminal, wherein the setting terminal is coupled to the voltage detection unit and sets the threshold voltage through a variable resistor. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record. The following is an examiner’s statement of reasons for allowance of claim 7: The prior art does not disclose that the voltage detection unit comprises a logic circuit, the logic circuit is coupled to the comparator and outputs a control signal according to the comparison result, and the voltage detection unit converts the control terminal voltage to the low-level voltage according to the control signal. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record. The following is an examiner’s statement of reasons for allowance of claim 8: The prior art does not further comprise a voltage drive unit, wherein the voltage drive unit is coupled to the control terminal, generates and outputs the control terminal voltage to the control terminal to change the control terminal voltage. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DHARTI PATEL whose telephone number is (571)272-8659. The examiner can normally be reached M - F 9 AM - 5 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. DHARTI PATEL Primary Examiner Art Unit 2836 /DHARTI H PATEL/Primary Examiner, Art Unit 2838
Read full office action

Prosecution Timeline

Jan 24, 2025
Application Filed
Aug 20, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
95%
With Interview (+7.7%)
2y 3m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1266 resolved cases by this examiner. Grant probability derived from career allowance rate.

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