Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 07/26/2026 have been fully considered but they are respectfully deemed not persuasive.
On page 1 of the remarks, it is alleged that the Office action’s statements and accompanying table “does not identify, for each pending claim, the particular cited patent claim or combination of patent claims alleged to render that pending claim unpatentable. Nor does the rejection analyze each pending claim as a whole, identify the differences between the claim and the cited patent claims or claims, or explain why those differences would have rendered the pending claim an obvious variation of the cited patented subject matter.” Examiner interprets the pending claims, either individually or in combination with other pending claims, are verbatim to the cited patented subject matter claims. For instance, pending claims 1, 2, 4 in combination contain claim language verbatim to cited patented subject matter claim 1 and pending claim 3 is verbatim to cited patented subject matter claim 11. Examiner asks Applicant to point out any specific differences that can be found between Applicant’s claimed invention and the cited patented case. Due to the reasons provided above, the rejections are maintained.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 6, 7, 10-13, 16, 17, and 20 of U.S. Patent No. 12242343. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations of the claimed invention are fully contained in the patented case. Furthermore, the pending claims are nothing more than an obvious system designed to perform the patented memory device. See table below. Therefore, the pending claims would have been obvious to a person having ordinary skill in the art at the time this invention was made, given the patented claims.
19036514
US 12242343
1. A memory device, comprising: one or more components configured to: receive, from a host device via a command address (CA) bus and during a unit interval, a set of CA bits; receive, from the host device via a parity bus and during the unit interval, a first parity bit that is based on the set of CA bits and a parity generation process; generate a second parity bit based on the set of CA bits and the parity generation process; compare the first parity bit and the second parity bit; and selectively transmit an alert signal to the host device based on a result of comparing the first parity bit and the second parity bit.
2. The memory device of claim 1, wherein the alert signal is transmitted to the host device via a unidirectional alert bus different than the CA bus.
4. The memory device of claim 1, wherein: the set of bits is associated with a CA word, the CA word includes a plurality of sets of CA bits, and each set of CA bits corresponds to a portion of the CA word that is received over a respective unit interval of a plurality of unit intervals for receiving the CA word.
1. A memory device, comprising: one or more components configured to: receive, from a host device via a command address (CA) bus and during a unit interval, a set of CA bits associated with a CA word, wherein the CA word includes a plurality of sets of CA bits, each set of CA bits corresponding to a portion of the CA word that is received over a respective unit interval of a plurality of unit intervals for receiving the CA word; receive, from the host device via a parity bus and during the unit interval, a first parity bit that is based on the set of CA bits and a parity generation process; generate a second parity bit based on the set of CA bits and the parity generation process; compare the first parity bit and the second parity bit; and selectively transmit an alert signal to the host device via a unidirectional alert bus and based on a result of comparing the first parity bit and the second parity bit, wherein the unidirectional alert bus is different than the CA bus
3. The memory device of claim 2, wherein the unidirectional alert bus is different than the parity bus.
11. The memory device of claim 1, wherein the unidirectional alert bus is different than the parity bus.
5. The memory device of claim 4, wherein each unit interval of the plurality of unit intervals comprises a first transmission via the CA bus that includes a respective set of CA bits of the plurality of sets of CA bits associated with the CA word and a second transmission via the parity bus that includes a parity bit that is based on the respective set of CA bits, wherein the first transmission is concurrent with the second transmission.
2. The memory device of claim 1, wherein each unit interval of the plurality of unit intervals comprises a first transmission via the CA bus that includes a respective set of CA bits of the plurality of sets of CA bits associated with the CA word and a second transmission via the parity bus that includes a parity bit that is based on the respective set of CA bits, wherein the first transmission is concurrent with the second transmission.
6. The memory device of claim 4, wherein the one or more components, to compare the first parity bit and the second parity bit, are configured to compare, for each set of CA bits associated with the CA word that is received over a respective unit interval of the plurality of unit intervals, a first parity bit that is received from the host device based on the set of CA bits and the parity generation process and a second parity bit that is generated by the memory device based on the set of CA bits and the parity generation process.
3. The memory device of claim 1, wherein the one or more components, to compare the first parity bit and the second parity bit, are configured to compare, for each set of CA bits associated with the CA word that is received over a respective unit interval of the plurality of unit intervals, a first parity bit that is received from the host device based on the set of CA bits and the parity generation process and a second parity bit that is generated by the memory device based on the set of CA bits and the parity generation process.
7. The memory device of claim 4, wherein the one or more components are configured to generate the CA word based on receiving the plurality of sets of CA bits over the plurality of unit intervals.
6. The memory device of claim 1, wherein the one or more components are configured to generate the CA word based on receiving the plurality of sets of CA bits over the plurality of unit intervals.
8. The memory device of claim 7, wherein the one or more components, to compare the first parity bit and the second parity bit, are configured to compare a first set of parity bits that are received from the host device based on the CA word and the parity generation process and a second set of parity bits that are generated by the memory device based on the CA word and the parity generation process.
7. The memory device of claim 6, wherein the one or more components, to compare the first parity bit and the second parity bit, are configured to compare a first set of parity bits that are received from the host device based on the CA word and the parity generation process and a second set of parity bits that are generated by the memory device based on the CA word and the parity generation process.
9. The memory device of claim 1, wherein the one or more components, to receive the set of CA bits via the CA bus during the unit interval, are configured to receive a first bit of the set of CA bits via a first pin of the CA bus and a second bit of set of CA bits via a second pin of the CA bus during the unit interval.
10. The memory device of claim 1, wherein the one or more components, to receive the set of CA bits via the CA bus during the unit interval, are configured to receive a first bit of the set of CA bits via a first pin of the CA bus and a second bit of the set of CA bits via a second pin of the CA bus during the unit interval.
10. A system comprising: a host device configured to: transmit, to a memory device via a command address (CA) bus and during a unit interval, a set of CA bits; generate a first parity bit based on the set of CA bits and a parity generation process; and transmit, to the memory device via a parity bus and during the unit interval, the first parity bit; and the memory device, wherein the memory device is configured to: receive, from the host device via the CA bus and during the unit interval, the set of CA bits; receive, from the host device via the parity bus and during the unit interval, the first parity bit; generate a second parity bit based on the set of CA bits and the parity generation process; compare the first parity bit and the second parity bit; and selectively transmit an alert signal to the host device based on a result of comparing the first parity bit and the second parity bit.
11. The system of claim 10, wherein the alert signal is transmitted to the host device via a unidirectional alert bus different than the CA bus.
13. The system of claim 10, wherein: the set of bits is associated with a CA word, the CA word includes a plurality of sets of CA bits, and each set of CA bits corresponds to a portion of the CA word that is received over a respective unit interval of a plurality of unit intervals for receiving the CA word.
12. A system comprising: a host device configured to: transmit, to a memory device via a command address (CA) bus and during a unit interval, a set of CA bits associated with a CA word, wherein the CA word includes a plurality of sets of CA bits, each set of CA bits corresponding to a portion of the CA word that is transmitted over a respective unit interval of a plurality of unit intervals for transmitting the CA word; generate a first parity bit based on the set of CA bits and a parity generation process; and transmit, to the memory device via a parity bus and during the unit interval, the first parity bit; and the memory device, wherein the memory device is configured to: receive, from the host device via the CA bus and during the unit interval, the set of CA bits; receive, from the host device via the parity bus and during the unit interval, the first parity bit; generate a second parity bit based on the set of CA bits and the parity generation process; compare the first parity bit and the second parity bit; and selectively transmit an alert signal to the host device via a unidirectional alert bus and based on a result of comparing the first parity bit and the second parity bit, wherein the unidirectional alert bus is different than the CA bus.
12. The system of claim 11, wherein the unidirectional alert bus is different than the parity bus.
11. The memory device of claim 1, wherein the unidirectional alert bus is different than the parity bus.
14. The system of claim 13, wherein each unit interval of the plurality of unit intervals comprises a first transmission via the CA bus that includes a respective set of CA bits of the plurality of sets of CA bits associated with the CA word and a second transmission via the parity bus that includes a parity bit that is based on the respective set of CA bits, wherein the first transmission is concurrent with the second transmission.
2. The memory device of claim 1, wherein each unit interval of the plurality of unit intervals comprises a first transmission via the CA bus that includes a respective set of CA bits of the plurality of sets of CA bits associated with the CA word and a second transmission via the parity bus that includes a parity bit that is based on the respective set of CA bits, wherein the first transmission is concurrent with the second transmission.
15. The system of claim 13, wherein the memory device, to compare the first parity bit and the second parity bit, is configured to compare, for each set of CA bits associated with the CA word that is received over a respective unit interval of the plurality of unit intervals, a first parity bit that is received from the host device based on the set of CA bits and the parity generation process and a second parity bit that is generated by the memory device based on the set of CA bits and the parity generation process.
13. The system of claim 12, wherein the memory device, to compare the first parity bit and the second parity bit, is configured to compare, for each set of CA bits associated with the CA word that is received over a respective unit interval of the plurality of unit intervals, a first parity bit that is received from the host device based on the set of CA bits and the parity generation process and a second parity bit that is generated by the memory device based on the set of CA bits and the parity generation process.
16. The system of claim 13, wherein the memory device is configured to generate the CA word based on receiving the plurality of sets of CA bits over the plurality of unit intervals.
16. The system of claim 12, wherein the memory device is configured to generate the CA word based on receiving the plurality of sets of CA bits over the plurality of unit intervals.
17. The system of claim 16, wherein the memory device, to compare the first parity bit and the second parity bit, is configured to compare a first set of parity bits that are received from the host device based on the CA word and the parity generation process and a second set of parity bits that are generated by the memory device based on the CA word and the parity generation process.
17. The system of claim 16, wherein the memory device, to compare the first parity bit and the second parity bit, is configured to compare a first set of parity bits that are received from the host device based on the CA word and the parity generation process and a second set of parity bits that are generated by the memory device based on the CA word and the parity generation process.
18. The system of claim 10, wherein the memory device, to receive the set of CA bits via the CA bus during the unit interval, is configured to receive a first bit of the set of CA bits via a first pin of the CA bus and a second bit of set of CA bits via a second pin of the CA bus during the unit interval.
10. The memory device of claim 1, wherein the one or more components, to receive the set of CA bits via the CA bus during the unit interval, are configured to receive a first bit of the set of CA bits via a first pin of the CA bus and a second bit of the set of CA bits via a second pin of the CA bus during the unit interval.
19. A method performed by a memory device, comprising: receiving, from a host device via a command address (CA) bus and during a unit interval, a set of CA bits; receiving, from the host device via a parity bus and during the unit interval, a first parity bit that is based on the set of CA bits and a parity generation process; generating a second parity bit based on the set of CA bits and the parity generation process; and transmitting an alert signal to the host device based on a result of comparing the first parity bit and the second parity bit.
20. The method of claim 19, wherein the alert signal is transmitted to the host device via a unidirectional alert bus different than the CA bus.
20. A method performed by a memory device, comprising: receiving, from a host device via a command address (CA) bus and during a unit interval of a plurality of unit intervals, a set of CA bits associated with a CA word; receiving, from the host device via a parity bus and during the unit interval, a first parity bit that is based on the set of CA bits and a parity generation process; generating a second parity bit based on the set of CA bits and the parity generation process; and transmitting an alert signal to the host device, via a unidirectional alert bus, based on a result of comparing the first parity bit and the second parity bit, wherein the unidirectional alert bus is different than the CA bus.
Closest Prior Arts of Record
Bains (US Pat. Pub. 20090313533) discloses host 110 transfers data frames and corresponding CRC frames to memory device 120 via DQ bus 104. Bains further discloses generating a local CRC checksum that is compared with a second CRC checksum and sending an error signal to the host if the checksums do not match.
Examiner’s Note
There are no prior art(s) rejections in this Office Action. However, examiner will further consider and update search to determine merits of the claims once Applicant’s fix the above nonstatutory double patent rejections.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEFFREY A YANG whose telephone number is (703)756-1447. The examiner can normally be reached Monday - Friday 8:30 a.m. - 5:30 p.m. PST.
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/JEFFREY ANDREW YANG/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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