DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on January 24, 2025 has been fully considered by the examiner.
Specification
3. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Nonvolatile Storage Device and Readout Circuit with Multiple Read Modes.”
Claim Rejections - 35 USC § 112
4. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
5. Claims 2 and 4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation, “a register that allows setting as to whether the readout circuit is operated in the first mode or the second mode from outside.” It is unclear to what “from outside” refers (e.g., from outside the readout circuit, register, etc.).
For the purpose of this action, “from outside” shall be interpreted as “from outside the nonvolatile storage device.”
Claim 4 recites the limitation, “a register that allows setting as to whether the readout circuit is operated in the first mode, the second mode, or the third mode from outside.” It is unclear to what “from outside” refers (e.g., from outside the readout circuit, register, etc.).
For the purpose of this action, “from outside” shall be interpreted as “from outside the nonvolatile storage device.”
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
7. Claims 1, 3, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Kurafuji, et al (US 20180277214 A1), hereinafter Kurafuji, in view of Takahashi (US 20120106258 A1).
Regarding independent claim 1, Kurafuji teaches a nonvolatile storage device comprising:
a memory cell array (FIG. 2, 110; ¶[0033]) having a plurality of nonvolatile memory cells (FIG. 2, memory cell pairs 150; ¶[0039]) including a first memory cell (FIG. 2, M1a of 150) and a second memory cell (FIG. 2, M1b of 150); and
a readout circuit (FIG. 2, sense amplifier circuit 107; ¶[0032]) reading out data from the memory cell array via a first node and a second node (FIG. 2, input nodes to SA1), wherein in a first mode (complementary read mode; ¶[0031]), the readout circuit reads out complementary data stored in the first memory cell and the second memory cell by comparing a first detection current flowing through the first memory cell electrically coupled to the first node with a second detection current flowing through the second memory cell electrically coupled to the second node (¶[0041] teaches “bit lines BL are connected to the sense amplifier SA1 so as to sense a current difference between the memory cell M1a and the memory cell M1b” and ¶[0042] teaches “The sense amplifier SA1 is a circuit that determines the value of data stored in the data memory unit 150 by comparing a current (memory cell current) flowing through one memory cell M1a of the data memory unit 150 and a current (memory cell current) flowing through the other memory cell M1b of the data memory unit 150”; see also FIG 4), and
in a second mode (reference read mode; ¶[0050]; FIG. 3), the readout circuit reads out the complementary data by comparing a current [obtained by addition or subtraction of a first reference current to or from the first detection current] with the second detection current, or reads out the complementary data by comparing the first detection current with a current [obtained by addition or subtraction of a second reference current to or from the second detection current] (referencing FIG. 3, ¶[0051] teaches “discharge of the bit line BL by the memory cell current flowing through the memory cell M2a and discharge of the signal line IL by the reference current Iref are carried out by control of the sense amplifier control circuit 108. Then, at specified sense timing t2, the sense amplifier SA2 senses a voltage difference between the voltage of the bit line BL and the voltage of the signal line IL and thereby determines the value stored in the memory cell M2a.”).
Kurafuji does not teach the comparison current (FIG. 3, Iref) is obtained by addition or subtraction of a first reference current to or from the first detection current or by addition or subtraction of a second reference current to or from the second detection current.
Takahashi teaches the comparison current (FIG. 3, Iref) is obtained by addition or subtraction of a first reference current to or from the first detection current or by addition or subtraction of a second reference current to or from the second detection current (¶[0030] teaches “reference current Iref is set so as to cause a value obtained by subtracting a maximum value of the first cell current Icell(OFF) from a minimum value of the reference current Iref to become greater than a value obtained by subtracting a maximum value of the reference current Iref from a minimum value of the second cell current Icell(ON).” That is, “The reference current Iref is set to be greater than a middle value between a first cell current Icell(OFF) which flows when the memory cell is in the off-state and a second cell current Icell(ON) which flows when the memory cell is in the on-state and also to be smaller than the second cell current Icell(ON),” as taught in ¶[0029]).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Takahashi into the method of Kurafuji to include setting the reference current Iref to be greater than a middle value between a first cell current Icell(OFF) and a second cell current Icell(ON) and also to be smaller than the second cell current Icell(ON). The ordinary artisan would have been motivated to modify Kurafuji in the above manner for the purpose of securing the margin of the sense amplifier (Takahashi ¶[0053]).
Regarding claim 3, Kurafuji in view of Takahashi teaches the limitations of claim 1.
Kurafuji further teaches, wherein in a third mode, the readout circuit reads out data stored in the first memory cell by comparing the first detection current with the second reference current, or reads out data stored in the second memory cell by comparing the second detection current with the first reference current (this is the unmodified (not modified by Takahashi) read reference mode of Kurafuji as taught in ¶[0050-0051] and FIG. 3).
Regarding claim 7, Kurafuji in view of Takahashi teaches the limitations of claim 1.
Kurafuji further teaches an integrated circuit device comprising the nonvolatile storage device according to claim 1 (FIG. 10).
8. Claims 2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Kurafuji, et al (US 20180277214 A1), hereinafter Kurafuji, in view of Takahashi (US 20120106258 A1), and further in view of Nixon (US 5819305 A).
Regarding claim 2, Kurafuji in view of Takahashi teaches the limitations of claim 1.
Kurafuji does not teach a register that allows setting as to whether the readout circuit is operated in the first mode or the second mode from outside (Kurafuji teaches in ¶[0082] a command specification register accessible by a CPU external to the flash memory, but does not teach the register sets the first and second modes).
Nixon teaches a register that allows setting as to whether the readout circuit is operated in the first mode or the second mode from outside (FIG. 4; Col. 3, ll. 19-38 teach “FIG. 4 illustrates configuration circuit 80 as a register” and “Configuration circuit 80…may be write and/or read accessible by way of bus 22 from CPU 12 or external bus 24.” Abstract teaches “Memory (20) includes a configuration circuit (80) which selects one of the plurality of memory modes. Configuration circuit (80) provides configuration information to sense amplifier control circuit (72). Sense amplifier control circuit (72) provides control information to sense amplifiers (70) in order to place sense amplifiers (70) in one of a plurality of operating modes. In one embodiment, the plurality of operating modes of sense amplifiers (70) includes a complementary differential operating mode and a referenced differential operating mode.”).
Regarding claim 4, Kurafuji in view of Takahashi teaches the limitations of claim 3.
Kurafuji does not teach a register that allows setting as to whether the readout circuit is operated in the first mode, the second mode, or the third mode from outside (Kurafuji teaches in ¶[0082] a command specification register accessible by a CPU external to the flash memory, but does not teach the register sets the first, second, and third modes).
Nixon teaches a register that allows setting as to whether the readout circuit is operated in the first mode, the second mode, or the third mode from outside (FIG. 4; Col. 3, ll. 19-38 teach “FIG. 4 illustrates configuration circuit 80 as a register” and “Configuration circuit 80…may be write and/or read accessible by way of bus 22 from CPU 12 or external bus 24.” Abstract teaches “Memory (20) includes a configuration circuit (80) which selects one of the plurality of memory modes. Configuration circuit (80) provides configuration information to sense amplifier control circuit (72). Sense amplifier control circuit (72) provides control information to sense amplifiers (70) in order to place sense amplifiers (70) in one of a plurality of operating modes. In one embodiment, the plurality of operating modes of sense amplifiers (70) includes a complementary differential operating mode and a referenced differential operating mode.”).
Regarding claims 2 and 4, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Nixon into the method of Kurafuji to include a configuration circuit (register) that may be write and/or read accessible by way of an external bus. The ordinary artisan would have been motivated to modify Kurafuji in the above manner for the purpose of configuring operating modes in a memory circuit (Nixon Col. 1, ll. 28-30).
Allowable Subject Matter
9. Claims 5-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
10. The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 5, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein the readout circuit reads out the complementary data in the first mode, determines whether the first reference current is added to or subtracted from the first detection current or the second reference current is added to or subtracted from the second detection current based on the complementary data read out in the first mode, and reads out the complementary data in the second mode.
Regarding claim 6, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein the readout circuit determines whether the first reference current is added to or subtracted from the first detection current or the second reference current is added to or subtracted from the second detection current based on the complementary data written in the first memory cell and the second memory cell, and reads out the complementary data in the second mode.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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