DETAILED ACTION
The action is responsive to the following communications: the Application filed January 24, 2025 and the information disclosure statement (IDS) filed April 02, 2026.
Claims 1-20 are pending. Claims 1, 10 and 19 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 02, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to because:
Figures 1-5 should be designated by a legend such as –Prior Art—because only that which is old is illustrated. See MPEP 608.02(g).
Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-5, 7, 14, 17 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lim et al. (US 2023/0027955).
Regarding independent claim 1 and its method claim 10, Lim et al. disclose an apparatus comprising:
a memory circuit (see FIG. 3A) comprising at least one three-dimensional (3D) NAND memory component, the at least one 3D NAND memory component comprising a plurality of memory cells; and
an inductor comprising:
a first set of vias (see FIG. 8), each via of the first set of vias being conductive and having a central axis that is parallel to central axes of the other vias of the first set of vias, the first set of vias including at least a first via (e.g., BVIA2), a second via (BVIA1), and a third via (BVIA3);
a first lower (LM2a) connection electrically connecting the first via (BVIA2) and the second via (BVIA1); and
a first upper connection (CTW) electrically connecting the second via (BVIA1) and the third via (BVIA3),
wherein an electrical signal path continuously extends from the first via, to the first lower connection, to the second via, to the first upper connection, and the electrical signal path forms a first turn of the inductor (see e.g., FIG. 8 and accompanying disclosure).
Further, regarding method claim 10, MPEP 2112.02(I) instructs examiners, “Under the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986).” Here, the applied prior art product is identical to applicant’s disclosed product, and therefore is assumed, in accordance with MPEP 2112.02(I), to inherently perform the claimed process.
Regarding claim 4, which depends from claim 1, Lim et al. disclose the inductor further comprising: a second set of vias arranged in parallel orientation, the second set of vias including at least a fourth via, a fifth via, and a sixth via; a second lower connection electrically connecting the fourth via and the fifth via; and a second upper connection electrically connecting the fifth via and the sixth via, wherein a second electrical signal path extends from the fourth via, to the second lower connection, to the fifth via, to the second upper connection, and the second electrical signal path forms a second turn of the inductor (see FIG. 8 in FIG. 6, next to EX1 or FIG. 4, MCA2 considering a first set of vias in MCA1).
Regarding claim 5, which depends from claim 4, Lim et al. disclose the first turn of the inductor belongs to an outer solenoid and the second turn of the inductor belongs to an inner solenoid, and wherein the second set of vias being contained within the confines of the first set of vias, the first upper connection, and the first lower connection (FIG. 7).
Regarding claim 7, which depends from claim 1, Lim et al. disclose the first lower connection electrically connecting the first via and the second via further comprises: a first plurality of contacts, the first plurality of contacts connecting the first via to the first lower connection; and a second plurality of contacts, the second plurality of contacts connecting the first lower connection to the second via (FIGS. 10-13, metal contact, and accompanying disclosure, e.g., para. 0083-0084).
Regarding claim 14, which depends from claim 10, Lim et al. disclose the set of vias comprises a first row of vias and a second row of vias, where the first row of vias is parallel to the second row of vias (FIG. 8).
Regarding claim 17, which depends from claim 10, Lim et al. disclose the first turn of the inductor is a first turn of an outer solenoid of the inductor, further comprising: forming an inner solenoid, the inner solenoid being contained within the first set of vias, the first upper connection, and the first lower connection, the forming the inner solenoid comprising: forming a second set of vias arranged in parallel orientation, the second set of vias including at least a fourth via, a fifth via, and a sixth via; forming a second lower connection electrically connecting the fourth via and the fifth via; and forming a second upper connection electrically connecting the fifth via and the sixth via wherein an electrical path that extends from the fourth via, to the second lower connection, to the fifth via, to the second upper connection, forms a first turn of the inner solenoid (see FIG. 8 in FIG. 6, next to EX1 or FIG. 4, MCA2 considering a first set of vias in MCA1).
Further, regarding method claim 17, MPEP 2112.02(I) instructs examiners, “Under the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986).” Here, the applied prior art product is identical to applicant’s disclosed product, and therefore is assumed, in accordance with MPEP 2112.02(I), to inherently perform the claimed process.
Regarding independent claim 19, Lim et al. disclose an integrated circuit-based inductor comprising:
an outer solenoid comprising:
a first set of vias (see FIG. 8) arranged in parallel orientation, the first set of vias including at least a first via (e.g., BVIA2), a second via (BVIA1), and a third via (BVIA3);
a first lower connection (LM2a) electrically connecting the first via (BVIA2) and the second via (BVIA1); and
a first upper connection (CTW) electrically connecting the second via (BVIA1) and the third via (BVIA3),
wherein an electrical path that extends from the first via, to the first lower connection, to the second via, to the first upper connection, forms a first turn of the outer solenoid (see e.g., FIG. 8 and accompanying disclosure); and
an inner solenoid comprising:
a second set of vias (see FIG. 8 in FIG. 6, next to EX1 or FIG. 4, MCA2 considering a first set of vias in MCA1) arranged in parallel orientation, the second set of vias including at least a fourth via (FIG. 8: BVIA2), a fifth via (BVIA1), and a sixth via (BVIA3);
a second lower connection (LM2a) electrically connecting the fourth via and the fifth via; and
a second upper connection (CTW) electrically connecting the fifth via and the sixth via,
wherein an electrical path that extends from the fourth via, to the second lower connection, to the fifth via, to the second upper connection, forms a first turn of the inner solenoid (see FIGS. 6-8 and accompanying disclosure).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 6 and 20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lim et al. (US 2023/0027955) in view of Yu et al. (US 2023/0065769).
Regarding claims 2 and 20, Lim et al. teach the limitations of claims 1 and 19, respectively.
Lim et al. are silent with respect to a ferromagnetic core disposed at least partially inside the first turn of the inner solenoid.
Yu et al. teach the deficiencies in e.g., FIG. 19 and accompanying disclosure, i.e., ferromagnetic layers 124 disposed inside through-via CV (The CVs are shown in FIGS 16-18)
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Yu et al. to the teaching of Lim et al. such that a memory, as taught by Lim et al., utilizes a ferromagnetic layers, as taught by Yu et al., for the purpose of establishing magnetic field through the contact vias.
Regarding claim 3, Lim et al. and Yu et al., as combined, teach the limitations of claim 2.
Lim et al. further teach the at least one 3D NAND memory component further comprises at least one oxide layer and at least one nitride layer, and wherein the first set of vias of the inductor extend through the at least one oxide layer and the at least one nitride layer (e.g., para. 0056: ONO structure; further it’s a well-known technology in a 3D NAND flash memory).
Regarding claim 6, Lim et al. teach the limitations of claim 4.
Lim et al. are silent with respect to the inductor further comprises: a ferromagnetic core contained within the confines of the second set of vias, the second upper connection, and the second lower connection.
Yu et al. teach the deficiencies in e.g., FIG. 19 and accompanying disclosure, i.e., ferromagnetic layers 124 disposed inside through-via CV (The CVs are shown in FIGS 16-18)
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Yu et al. to the teaching of Lim et al. such that a memory, as taught by Lim et al., utilizes a ferromagnetic layers, as taught by Yu et al., for the purpose of establishing magnetic field through the contact vias.
Claims 8-9, 11-13, 15-16 and 18 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lim et al. (US 2023/0027955).
Regarding claim 8, Lim et al. teach the limitations of claim 7.
Lim et al. are silent with respect to each contact in the first plurality of contacts has a cross-sectional shape of square, longitudinal rectangle, or transverse rectangle.
However, the claimed shape of contacts is a well-known technology for a type of memory structure for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize some shape of contacts because these conventional technology are well established in the art of the memory devices.
Regarding claims 9 and 18, Lim et al. teach the limitations of claims 1 and 10, respectively.
Lim et al. are silent with respect to a boost converter configured to supply voltage to the memory circuit, the boost converter comprising the inductor..
However, the claimed limitation of PMIC is a well-known technology for a type of memory for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize boost converter in PMIC because these conventional technology are well established in the art of the memory devices.
Regarding claims 11-12, Lim et al. teach the limitations of claim 10.
Lim et al. further teach forming the first lower connection further comprises: applying a hard mask to a top surface; etching at least one lower-connection-shaped hole into the hard mask; and filling the at least one lower-connection-shaped hole with tungsten to form the first lower connection; and forming the first upper connection further comprises: applying a hard mask to the top surface of the first set of vias; etching at least one upper-connection-shaped hole into the hard mask; and filling the at least one upper-connection shaped hole with a conductive material to form the first upper connection (see e.g., FIG. 8 and accompanying disclosure).
Lim et al. do not explicitly disclose the fabrication process of NAND memory.
However, Lim et al. device is the same as a device described in the specification for carrying out the claimed method, and it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986).” Here, the applied prior art product is identical to applicant’s disclosed product, and therefore is assumed, in accordance with MPEP 2112.02(I), to inherently perform the claimed process.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize memory manufacturing process because these conventional technology are well established in the art of the memory devices.
Regarding claim 13, Lim et al. teach the limitations of claim 10.
Lim et al. do not explicitly disclose the first set of vias are formed during fabrication of vias of the 3D NAND circuit on the first die.
However, Lim discloses a semiconductor 3D NAND circuit, and it is a well-known technology that NAND technology manufacture on a die, more specifically, the first die in the stacked die structure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize memory manufacturing process because these conventional technology are well established in the art of the memory devices.
Regarding claims 15-16, Lim et al. teach the limitations of claim 14.
Lim et al. further teach forming a block of oxide; etching the block of oxide to form an oblong hole oriented between the first row of vias and the second row of vias; and at least partially filling the oblong hole with a ferromagnetic material to form a magnetic core; and filling the remainder of the oblong hole with an oxide (see FIGS. 6-13 and accompanying disclosure).
Lim et al. do not explicitly disclose the fabrication process of NAND memory.
However, Lim et al. device is the same as a device described in the specification for carrying out the claimed method, and it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986).” Here, the applied prior art product is identical to applicant’s disclosed product, and therefore is assumed, in accordance with MPEP 2112.02(I), to inherently perform the claimed process.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize memory manufacturing process because these conventional technology are well established in the art of the memory devices.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached on 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
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