DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 3, 18, 20, and 21 have been amended as per Applicant’s amendment filed on March 5, 2026. Claims 2 and 19 have been canceled. Claims 1, 3-18, and 20-22 are pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4 of copending Application No. 18/822,222 in view of Yang (US 2023/0267882 A1, Published August 24, 2023) and Kim2 (US 2020/0111403 A1, Published April 9, 2020).
Present Application
US Application 18/822,222
1. A pixel circuit comprising:
a light emitting element;
a constant current generation (CCG) circuit configured to generate a fixed driving current based on a CCG data voltage of a data voltage, a second high power voltage, and a low power voltage to provide the fixed driving current to the light emitting element; and
a pulse width modulation (PWM) circuit configured to control a generation time of the fixed driving current based on a PWM data voltage of the data voltage, a sweep voltage, and a first high power voltage different from the second high power voltage,
wherein the PWM circuit comprises: a first transistor comprising a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node;
a second transistor comprising a gate electrode configured to receive a first write gate signal, a first electrode configured to receive the data voltage, and a second electrode connected to the second node; and
a first capacitor comprising a first electrode configured to receive a swing voltage and a second electrode connected to the first node, and
wherein the CCG circuit comprises:
a seventh transistor comprising a gate electrode connected to a fourth node, a first electrode configured to receive the second high power voltage, and a second electrode connected to a fifth node;
an eighth transistor comprising a gate electrode configured to receive a second write gate signal, a first electrode configured to receive the data voltage, and a second electrode connected to a sixth node; and
a second capacitor comprising a first electrode connected to the sixth node and a second electrode connected to the fourth node
a third capacitor comprising a first electrode configured to receive the second high power voltage and a second electrode connected to the sixth node,
wherein the first electrode of the second transistor and the first electrode of the eighth transistor are connected to each other.
1. An electronic device comprising: a processor configured to provide input image data; and a display device configured to receive the input image data from the processor, and to display an image based on the input image data the display device comprising a plurality of pixels, each of the plurality of pixels comprising:
a light emitting element;
a constant current generation (CCG) circuit configured to provide a constant driving current to the light emitting element based on a constant current data voltage and a power supply voltage; and a connection switch configured to connect the PWM circuit to the CCG circuit,
a pulse width modulation (PWM) circuit configured to control an emission time of the light emitting element based on a PWM data voltage, a sweep voltage, and a reference voltage;
wherein the light emitting elements of the plurality of pixels substantially simultaneously start emitting light at a start time point of an emission period,
wherein, in each of the plurality of pixels, the PWM circuit transfers the reference voltage to the CCG circuit through the connection switch at a time point corresponding to a voltage level of the PWM data voltage, and the CCG circuit causes the light emitting element to stop emitting light in response to the reference voltage, and
wherein the reference voltage is applied to the PWM circuit, the power supply voltage is applied to the CCG circuit, and the reference voltage is higher than or equal to the power supply voltage.
[Claim 4] 4. The display device of claim 1, wherein the PWM circuit comprises: a first transistor including a gate, a first terminal, and a second terminal;
a second transistor including a gate configured to receive a first writing signal, a first terminal connected to a first data line, and a second terminal connected to the first terminal of the first transistor;
a third transistor including a gate configured to receive a first emission signal, a first terminal connected to a line associated with transferring the reference voltage, and a second terminal connected to the first terminal of the first transistor; a fourth transistor including a gate configured to receive a third writing signal, a first terminal connected to the second terminal of the first transistor, and a second terminal connected to the gate of the first transistor; and
a first capacitor including a first electrode connected to a line associated with transferring the sweep voltage and a second electrode connected to the gate of the first transistor.
Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of claim 1 overlaps the scope of claims 1, 5 or US Application 18/822,222, and vice-versa with the exception that claims 1, 4 of US Application 18/822,222 do not disclose the claimed aspects of: “wherein the CCG circuit comprises: a seventh transistor comprising a gate electrode connected to a fourth node, a first electrode configured to receive the second high power voltage, and a second electrode connected to a fifth node; an eighth transistor comprising a gate electrode configured to receive a second write gate signal, a first electrode configured to receive the data voltage, and a second electrode connected to a sixth node; and a second capacitor comprising a first electrode connected to the sixth node and a second electrode connected to the fourth node; and a third capacitor comprising a first electrode configured to receive the second high power voltage and a second electrode connected to the sixth node, wherein the first electrode of the second transistor and the first electrode of the eighth transistor are connected to each other.”
However, Yang does disclose wherein the CCG circuit comprises: a seventh transistor comprising a gate electrode connected to a fourth node, a first electrode configured to receive the second high power voltage, and a second electrode connected to a fifth node (Yang at Fig. 4, transistor T1);
an eighth transistor comprising a gate electrode configured to receive a second write gate signal, a first electrode configured to receive the data voltage, and a second electrode connected to a sixth node (Yang at Fig. 4, transistor T2. Node N1 is analogous to a sixth node); and
a second capacitor comprising a first electrode connected to the sixth node and a second electrode connected to the fourth node (Yang at Fig. 4, capacitor Cst2. Node N2 is analogous to a fourth node),
a third capacitor comprising a first electrode configured to receive the second high power voltage and a second electrode connected to the sixth node (Yang at Fig. 4, capacitor Cst1)
US Application 18/822,222 discloses a base display LED pixel circuit upon which the claimed invention is an improvement. Yang discloses a comparable display LED pixel circuit which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to US Application 18/822,222 the teachings of Yang for the predictable result of improving reliability (Yang at ¶ [0006]).
The combination of US Application 18/822,222 and Yang does not disclose that the first electrode of the second transistor and the first electrode of the eighth transistor are connected to each other.
However, Kim2 does disclose that wherein the first electrode of the second transistor and the first electrode of the eighth transistor are connected to each other (Kim2 at Fig. 9, data line Sig<m> is electrically connected to transistor 323 of PWM circuit 320 and to transistor 315 of PAM driving circuit 310)).
The combination of US Application 18/822,222 and Yang discloses a base display LED pixel circuit upon which the claimed invention is an improvement. Kim2 discloses a comparable display LED pixel circuit which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to the combination of US Application 18/822,222 and Yang the teachings of Kim2 for the predictable result of providing improved color reproducibility (Kim2 at ¶ [0006]).
This is a provisional nonstatutory double patenting rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-18, 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2021/0210003 A1, Published July 8, 2021) in view of Yang (US 2023/0267882 A1, Published August 24, 2023) and Kim2 (US 2020/0111403 A1, Published April 9, 2020).
As to claim 1, Kim discloses a pixel circuit comprising:
a light emitting element (Kim at Figs. 12-12, light emitting element 120);
a constant current generation (CCG) circuit configured to generate a fixed driving current based on a CCG data voltage of a data voltage, a second high power voltage, and a low power voltage to provide the fixed driving current to the light emitting element (Kim at Figs. 11-12, constant current generator 112, VDD_PAM, VSS; ¶ 0189], [0221]); and
a pulse width modulation (PWM) circuit configured to control a generation time of the fixed driving current based on a PWM data voltage of the data voltage, a sweep voltage, and a first high power voltage different from the second high power voltage (Kim at Figs. 11-12, PWM circuit 111, VDD_PWM),
wherein the PWM circuit comprises: a first transistor comprising a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node (Kim at Fig. 12, transistor T3);
a second transistor comprising a gate electrode configured to receive a first write gate signal, a first electrode configured to receive the data voltage, and a second electrode connected to the second node (Kim at Fig. 12, transistor T2); and
a first capacitor comprising a first electrode configured to receive a swing voltage and a second electrode connected to the first node (Kim at Fig. 12, capacitor C1 and Sweep(n)), and
wherein the CCG circuit comprises: a seventh transistor comprising a gate electrode connected to a fourth node, a first electrode configured to receive the second high power voltage, and a second electrode connected to a fifth node (Kim at Fig. 12, transistor T10).1
Kim does not disclose an eighth transistor comprising a gate electrode configured to receive a second write gate signal, a first electrode configured to receive the data voltage, and a second electrode connected to a sixth node; and a second capacitor comprising a first electrode connected to the sixth node and a second electrode connected to the fourth node, and a third capacitor comprising a first electrode configured to receive the second high power voltage and a second electrode connected to the sixth node,
However, Yang does disclose an eighth transistor comprising a gate electrode configured to receive a second write gate signal, a first electrode configured to receive the data voltage, and a second electrode connected to a sixth node (Yang at Fig. 4, transistor T2. Node N1 is analogous to a sixth node); and
a second capacitor comprising a first electrode connected to the sixth node and a second electrode connected to the fourth node (Yang at Fig. 4, capacitor Cst2. Node N2 is analogous to a fourth node).
a third capacitor comprising a first electrode configured to receive the second high power voltage and a second electrode connected to the sixth node (Yang at Fig. 4, capacitor Cst1).
Kim discloses a base display LED pixel circuit upon which the claimed invention is an improvement. Yang discloses a comparable display LED pixel circuit which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Kim the teachings of Yang for the predictable result of improving reliability (Yang at ¶ [0006]).
The combination of Kim and Yang does not disclose that the first electrode of the second transistor and the first electrode of the eighth transistor are connected to each other.
However, Kim2 does disclose that wherein the first electrode of the second transistor and the first electrode of the eighth transistor are connected to each other (Kim2 at Fig. 9, data line Sig<m> is electrically connected to transistor 323 of PWM circuit 320 and to transistor 315 of PAM driving circuit 310)).
The combination of Kim and Yang discloses a base display LED pixel circuit upon which the claimed invention is an improvement. Kim2 discloses a comparable display LED pixel circuit which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to the combination of Kim and Yang the teachings of Kim2 for the predictable result of providing improved color reproducibility (Kim2 at ¶ [0006]).
As to claim 3, the combination of Kim, Yang, and Kim2 discloses the pixel circuit of claim 1, wherein the CCG circuit further comprises: a ninth transistor comprising a gate electrode configured to receive a compensation gate signal, a first electrode connected to the fifth node, and a second electrode connected to the fourth node (Yang at Fig. 4, transistor T3).
Kim discloses a base display LED pixel circuit upon which the claimed invention is an improvement. Yang discloses a comparable display LED pixel circuit which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Kim the teachings of Yang for the predictable result of improving reliability (Yang at ¶ [0006]).
As to claim 4, the combination of Kim, Yang, and Kim2 discloses the pixel circuit of claim 3, wherein the CCG circuit further comprises: an eleventh transistor comprising a gate electrode configured to receive a second initialization gate signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to the fourth node (Kim at Fig. 12, transistor T14).
As to claim 5, the combination of Kim, Yang, and Kim2discloses the pixel circuit of claim 4, wherein the light emitting element comprises an anode connected to the CCG circuit and a cathode configured to receive the low power voltage (Kim at Fig. 12, light emitting device 120), and
wherein the CCG circuit further comprises: a twelfth transistor comprising a gate electrode configured to receive an anode initialization gate signal, a first electrode configured to receive an anode initialization voltage, and a second electrode connected to the anode of the light emitting element (Yang at Fig. 12, transistor T4) .
Kim discloses a base display LED pixel circuit upon which the claimed invention is an improvement. Yang discloses a comparable display LED pixel circuit which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Kim the teachings of Yang for the predictable result of improving reliability (Yang at ¶ [0006]).
As to claim 6, the combination of Kim, Yang, and Kim2 discloses the pixel circuit of claim 5, wherein the seventh transistor and the twelfth transistor are P-type transistors, and the eighth transistor, the ninth transistor, and the eleventh transistor are N-type transistors (Kim at ¶ [0414]-[0415]).2
As to claim 7, the combination of Kim, Yang, and Kim2 discloses the pixel circuit of claim 5, wherein the seventh to ninth transistors, the eleventh transistor, and the twelfth transistor are P-type transistors (Kim at ¶ [0414]-[0415]).3
As to claim 8, the combination of Kim, Yang, and Kim2 discloses the pixel circuit of claim 5, wherein the compensation gate signal, the second write gate signal, and the second initialization gate signal are global scan signals (Kim at Fig. 12) (Yang at Fig. 4).
Kim discloses a base display LED pixel circuit upon which the claimed invention is an improvement. Yang discloses a comparable display LED pixel circuit which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Kim the teachings of Yang for the predictable result of improving reliability (Yang at ¶ [0006]).
As to claim 9, the combination of Kim, Yang, and Kim2 discloses the pixel circuit of claim 5, wherein the CCG circuit further comprises: a tenth transistor connected between the fifth node and the anode of the light emitting element and configured to be turned on in response to an emission signal (Kim at Fig. 12, transistor T15).4
As to claim 10, the combination of Kim, Yang, and Kim2 discloses the pixel circuit of claim 5, wherein the CCG circuit further comprises: a tenth transistor configured to receive the second high power voltage and connected to the first electrode of the seventh transistor, and configured to turn on in response to an emission signal (Kim at Fig. 12, transistor T15).5
As to claim 11, the combination of Kim, Yang, and Kim2 discloses the pixel circuit of claim 1, wherein the PWM circuit further comprises: a third transistor comprising a gate electrode configured to receive the first write gate signal, a first electrode connected to the third node, and a second electrode connected to the first node (Kim at Fig. 12, transistor T4).
As to claim 12, the combination of Kim, Yang, and Kim2 discloses the pixel circuit of claim 11, wherein the PWM circuit further comprises: a sixth transistor comprising a gate electrode configured to receive a first initialization gate signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to the first node (Kim at Fig. 12, transistor T12).
As to claim 13, the combination of Kim, Yang, and Kim2 discloses the pixel circuit of claim 12, wherein the PWM circuit further comprises: a fourth transistor comprising a gate electrode configured to receive an emission signal, a first electrode configured to receive the first high power voltage, and a second electrode connected to the second node (Kim at Fig. 12, transistor T1); and
a fifth transistor comprising a gate electrode configured to receive the emission signal, a first electrode connected to the third node, and a second electrode connected to the fourth node (Kim at Fig. 12, transistor T5).
As to claim 14, the combination of Kim, Yang, and Kim2 discloses the pixel circuit of claim 13, wherein the first transistor, the fourth transistor, and the fifth transistor are P-type transistors, and the second transistor, the third transistor, and the sixth transistor are N-type transistors (Kim at ¶ [0414]-[0415]).6
As to claim 15, the combination of Kim, Yang, and Kim2 discloses the pixel circuit of claim 13, wherein the first to sixth transistors are P-type transistors (Kim at ¶ [0414]-[0415]).7
As to claim 16, the combination of Kim, Yang, and Kim2 discloses the pixel circuit of claim 13, wherein the first write gate signal is a progressive scan signal, and the first write gate signal, the first initialization gate signal, and the emission signal are global scan signals (Kim at Fig. 12) (Yang at Fig. 4).
Kim discloses a base display LED pixel circuit upon which the claimed invention is an improvement. Yang discloses a comparable display LED pixel circuit which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Kim the teachings of Yang for the predictable result of improving reliability (Yang at ¶ [0006]).
As to claim 17, the combination of Kim, Yang, and Kim2 discloses the pixel circuit of claim 1, wherein the second high power voltage is lower than the first high power voltage (Kim at Fig. 11-12).
As to claim 18, Kim discloses a display device comprising: a display panel comprising a pixel circuit; and a display panel driver configured to drive the display panel (Kim at Figs. 4, 10, in particular),
wherein the pixel circuit comprises: a light emitting element (Kim at Figs. 12-12, light emitting element 120);
a constant current generation (CCG) circuit configured to generate a fixed driving current based on a CCG data voltage of a data voltage, a second high power voltage, and a low power voltage to provide the fixed driving current to the light emitting element (Kim at Figs. 11-12, constant current generator 112, VDD_PAM, VSS; ¶ 0189], [0221]); and
a pulse width modulation (PWM) circuit configured to control a generation time of the fixed driving current based on a PWM data voltage of the data voltage, a sweep voltage, and a first high power voltage different from the second high power voltage (Kim at Figs. 11-12, PWM circuit 111, VDD_PWM),
wherein the PWM circuit comprises: a first transistor comprising a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node (Kim at Fig. 12, transistor T3);
a second transistor comprising a gate electrode configured to receive a first write gate signal, a first electrode configured to receive the data voltage, and a second electrode connected to the second node (Kim at Fig. 12, transistor T2); and
a first capacitor comprising a first electrode configured to receive a swing voltage and a second electrode connected to the first node (Kim at Fig. 12, capacitor C1 and Sweep(n)), and
wherein the CCG circuit comprises: a seventh transistor comprising a gate electrode connected to a fourth node, a first electrode configured to receive the second high power voltage, and a second electrode connected to a fifth node (Kim at Fig. 12, transistor T10).8
Kim does not disclose an eighth transistor comprising a gate electrode configured to receive a second write gate signal, a first electrode configured to receive the data voltage, and a second electrode connected to a sixth node; and a second capacitor comprising a first electrode connected to the sixth node and a second electrode connected to the fourth node, a third capacitor comprising a first electrode configured to receive the second high power voltage and a second electrode connected to the sixth node.
However, Yang does disclose an eighth transistor comprising a gate electrode configured to receive a second write gate signal, a first electrode configured to receive the data voltage, and a second electrode connected to a sixth node (Yang at Fig. 4, transistor T2. Node N1 is analogous to a sixth node); and
a second capacitor comprising a first electrode connected to the sixth node and a second electrode connected to the fourth node (Yang at Fig. 4, capacitor Cst2. Node N2 is analogous to a fourth node),
a third capacitor comprising a first electrode configured to receive the second high power voltage and a second electrode connected to the sixth node (Yang at Fig. 4, capacitor Cst1).
Kim discloses a base display LED pixel circuit upon which the claimed invention is an improvement. Yang discloses a comparable display LED pixel circuit which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Kim the teachings of Yang for the predictable result of improving reliability (Yang at ¶ [0006]).
The combination of Kim and Yang does not disclose that the first electrode of the second transistor and the first electrode of the eighth transistor are connected to each other.
However, Kim2 does disclose that wherein the first electrode of the second transistor and the first electrode of the eighth transistor are connected to each other (Kim2 at Fig. 9, data line Sig<m> is electrically connected to transistor 323 of PWM circuit 320 and to transistor 315 of PAM driving circuit 310)).
The combination of Kim and Yang discloses a base display LED pixel circuit upon which the claimed invention is an improvement. Kim2 discloses a comparable display LED pixel circuit which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to the combination of Kim and Yang the teachings of Kim2 for the predictable result of providing improved color reproducibility (Kim2 at ¶ [0006]).
As to claim 20, the combination of Kim, Yang, and Kim2 discloses the display device of claim 18, wherein the CCG circuit further comprises: a ninth transistor comprising a gate electrode configured to receive a compensation gate signal, a first electrode connected to the fifth node, and a second electrode connected to the fourth node (Yang at Fig. 4, transistor T3).
Kim discloses a base display LED pixel circuit upon which the claimed invention is an improvement. Yang discloses a comparable display LED pixel circuit which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Kim the teachings of Yang for the predictable result of improving reliability (Yang at ¶ [0006]).
As to claim 21, Kim discloses an electronic device comprising a display device, the display device comprising: a display panel comprising a pixel circuit; and a display panel driver configured to drive the display panel (Kim at Figs. 4, 10, in particular),
wherein the pixel circuit comprises: a light emitting element (Kim at Figs. 12-12, light emitting element 120);
a constant current generation (CCG) circuit configured to generate a fixed driving current based on a CCG data voltage of a data voltage, a second high power voltage, and a low power voltage to provide the fixed driving current to the light emitting element (Kim at Figs. 11-12, constant current generator 112, VDD_PAM, VSS; ¶ 0189], [0221]); and
a pulse width modulation (PWM) circuit configured to control a generation time of the fixed driving current based on a PWM data voltage of the data voltage, a sweep voltage, a first high power voltage different from the second high power voltage, and a low power voltage (Kim at Figs. 11-12, PWM circuit 111, VDD_PWM, VSS),
wherein the PWM circuit comprises: a first transistor comprising a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node (Kim at Fig. 12, transistor T3);
a second transistor comprising a gate electrode configured to receive a first write gate signal, a first electrode configured to receive the data voltage, and a second electrode connected to the second node (Kim at Fig. 12, transistor T2); and
a first capacitor comprising a first electrode configured to receive a swing voltage and a second electrode connected to the first node Kim at Fig. 12, capacitor C1 and Sweep(n)), and
wherein the CCG circuit comprises: a seventh transistor comprising a gate electrode connected to a fourth node, a first electrode configured to receive the second high power voltage, and a second electrode connected to a fifth node (Kim at Fig. 12, transistor T10).9
Kim does not disclose an eighth transistor comprising a gate electrode configured to receive a second write gate signal, a first electrode configured to receive the data voltage, and a second electrode connected to a sixth node; and a second capacitor comprising a first electrode connected to the sixth node and a second electrode connected to the fourth node, a third capacitor comprising a first electrode configured to receive the second high power voltage and a second electrode connected to the sixth node.
However, Yang does disclose an eighth transistor comprising a gate electrode configured to receive a second write gate signal, a first electrode configured to receive the data voltage, and a second electrode connected to a sixth node (Yang at Fig. 4, transistor T2. Node N1 is analogous to a sixth node);
a second capacitor comprising a first electrode connected to the sixth node and a second electrode connected to the fourth node (Yang at Fig. 4, capacitor Cst2. Node N2 is analogous to a fourth node).
a third capacitor comprising a first electrode configured to receive the second high power voltage and a second electrode connected to the sixth node (Yang at Fig. 4, capacitor Cst1).
Kim discloses a base display LED pixel circuit upon which the claimed invention is an improvement. Yang discloses a comparable display LED pixel circuit which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to Kim the teachings of Yang for the predictable result of improving reliability (Yang at ¶ [0006]).
The combination of Kim and Yang does not disclose that the first electrode of the second transistor and the first electrode of the eighth transistor are connected to each other.
However, Kim2 does disclose that wherein the first electrode of the second transistor and the first electrode of the eighth transistor are connected to each other (Kim2 at Fig. 9, data line Sig<m> is electrically connected to transistor 323 of PWM circuit 320 and to transistor 315 of PAM driving circuit 310)).
The combination of Kim and Yang discloses a base display LED pixel circuit upon which the claimed invention is an improvement. Kim2 discloses a comparable display LED pixel circuit which has been improved in the same way as the claimed invention. Hence, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify or add to the combination of Kim and Yang the teachings of Kim2 for the predictable result of providing improved color reproducibility (Kim2 at ¶ [0006]).
As to claim 22, the combination of Kim, Yang, and Kim2 discloses the electronic device of claim 21, wherein the electronic device comprises a cellular phone, a video phone, a smart pad, a smart phone, a tablet PC, a car navigation system, a computer monitor, a laptop, or a head mounted display (HMD) device (Kim at ¶ [0195]).
Response to Arguments
Applicant’s arguments with respect to claims 1, 3-18, 20-22 have been considered but they are believed to be addressed above, and therefore, moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Sanjiv D Patel whose telephone number is (571)270-5731. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm.
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/Sanjiv D. Patel/Primary Examiner, Art Unit 2625
03/20/2026
1 See also Yang at Fig. 4, transistor T1.
2 See also Yang at ¶ [0084].
3 See also Yang at ¶ [0084].
4 See also Yang at Fig. 4, transistor T6.
5 See also Yang at Fig. 4, transistor T6.
6 See also Yang at ¶ [0084].
7 See also Yang at ¶ [0084].
8 See also Yang at Fig. 4, transistor T1.
9 See also Yang at Fig. 4, transistor T1.