Prosecution Insights
Last updated: September 29, 2026
Application No. 19/037,772

LEARNING MEMORY SYSTEMS AND METHODS

Final Rejection §101
Filed
Jan 27, 2025
Priority
Jun 03, 2020 — provisional 63/033,894 +1 more
Examiner
DARE, RYAN A
Art Unit
2132
Tech Center
2100 — Computer Architecture & Software
Assignee
University of Florida Research Foundation Inc.
OA Round
2 (Final)
76%
Grant Probability
Favorable
3-4
OA Rounds
1y 10m
Est. Remaining
84%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
449 granted / 591 resolved
+21.0% vs TC avg
Moderate +8% lift
Without
With
+8.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
19 currently pending
Career history
617
Total Applications
across all art units

Statute-Specific Performance

§101
6.5%
-33.5% vs TC avg
§103
48.7%
+8.7% vs TC avg
§102
31.7%
-8.3% vs TC avg
§112
8.9%
-31.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 591 resolved cases

Office Action

§101
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-30 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Claim 1 recites selecting, using one or more processors, locations of one or more memory subsystems components of the digital memory system for storage of one or more hives, wherein a hive of the one or more hives stores data of a particular modality; selecting, using the one or more processors, first locations of the hive for storage of one or more localities for the hive, wherein a locality of the one or more localities for the hive comprises one or more data units that are one or more of semantically related or interconnected based on a relation to each other; selecting, using the one or more processors, second locations of the hive for storage of at least one cue bank for the hive, wherein the at least one cue bank is configured to store cue objects configured to semantically link one or more data units across the one or more localities for the hive; generating, using the one or more processors and for the hive, an inter-data unit connectivity graph comprising a plurality of nodes and a plurality of edges, wherein a node of the plurality of nodes represents a cue object of the hive and an edge of the plurality of edges represents an association between a first node representing a first cue object and a second node representing a second cue object; and adjusting, using the one or more processors, the inter-data unit connectivity graph according to changes in associations between the cue objects of the hive, wherein the associations are one or more of generated, deleted, strengthened, or weakened based at least in part on memory operations over time.. These limitations are processes, that under their broadest reasonable interpretation, are performable in the mind and thus recite an abstract idea. The specification of parent application 17/336,944, incorporated by reference in its entirety as stated in par. 1 of the present application, is replete of humans mentally selecting various parameters and settings on which the system operates. See, for example, parent application paragraph 79, where a mapping may be user defined, parent application paragraph 80, where the decay rate is determined by a user, parent application paragraph 82, where parameters are changed manually by a user, parent application paragraph 100, where hyperparameters are changed by a user/admin, parent application paragraph 105, where hyperparameters are set/changed by the user during setup, parent application paragraphs 126, 135, 138, and 141, where various hyperparameters and cues are selected by the user, and parent application paragraph 169, where storage of certain types of data is specified by a user. The high level of generality of the claim language encompasses a user mentally selecting storage locations (hives) for certain types of information (i.e. images), and mentally selecting sub-storage areas (i.e. localities) for various semantically or otherwise related information – with or without the aid of pen and paper. This is akin to activities humans have routinely performed mentally, such as organizing a photo album into sub-topics: e.g. selecting a folder, box, or filing cabinet drawer for photos (i.e. a hive), and organizing the photos into specific folders (i.e. localities) for various related topics – such as birthday photos. Additionally, the limitation “selecting, using the one or more processors, second locations of each hive for storage of at least one cue bank for the hive, wherein the at least one cue bank is configured to store cues configured to semantically link one or more data units across the one or more localities for a particular hive” is performable in the human mind, perhaps with the aid of pen and paper. Applicant’s parent application specification, in paragraph 4, describes cues as patterns, and the examples provided are akin to labels or conceptual ideas easily maintained in the mind or on a sheet of paper (see parent application paragraph 85’s example of a cue “wolf” for describing an image with a wolf in it. In the photo organization example above, the cue bank limitation would encompass a label on the folder or a person mentally knowing that the bottom filing draw and the first folder held birthday photos. The claim includes the limitations “generating, using the one or more processors and for each hive of the one or more hives, an inter-data unit connectivity graph comprising a plurality of nodes and a plurality of edges. wherein each node of the plurality of nodes represents a cue object of the hive and an edge of the plurality of edges represents an association between a first node representing a first cue object and a second node representing a second cue object” and “adjusting, using the one or more processors, the inter-data unit connectivity graph according to changes in associations between the cue objects of the hive, wherein the associations are one or more of generated, deleted, strengthened, or weakened based at least in part on memory operations over time,” which amounts to an abstract idea, as it is an example of a mental process and/or a mathematical concept. In mathematics, graph theory is the study of graphs which are mathematical structures to model pairwise relationships between objects. The cue objects are the nodes of a graph. This is described in paragraph 87 of the present specification: “Each hive may have it’s own cue bank which stores cue objects arranged as a graph.” As described in paragraph 87 of the present application and illustrated in figure 1D, the associations are the edges of a graph. Generating and adjusting the graph can be performed mentally, or with the aid of pen and paper. Applicant’s figures 1D and 3D show how one can generate and adjust a graph using a pen and paper. In summary, a graph is a mathematical concept and generating and adjusting the graph is a mental process, as it can be done entirely in the mind, or at the very least, with the aid of pen and paper, as Applicant has demonstrated. Thus, the claim is directed to an abstract idea. This judicial exception is not integrated into a practical application because it only teaches using at least one processor and one memory storing instructions, as well as a digital memory, for performing the configuring and adjusting limitations. The processors, memory, and digital memory are recited at a high-level of generality (i.e. a generic processor and memory performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using a generic computer component. Accordingly, the additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea. The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of using a processor and memory/digital memory to perform both the generating and adjusting steps amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The claim is not patent eligible. As discussed above, while the generating and adjusting the graph according to changes in associations limitation amounts to mental steps, were it to be interpreted as not a mental step, it at the very least amounts to an additional element example of “apply it” rationale. The claim recites only the idea of a solution or outcome without reciting details of how the solution to a problem is accomplished (See MPEP 2106.05). In either case, the claim is not patent eligible. Further evidence that the claim limitations are performable in the human mind is Applicant’s stated admissions that the they are performable in the human mind. For example, paragraph 79 of the parent specification states that localization exists in the human brain, and Applicant’s concept of storing data at specific localities is based on the idea of localization in the human brain. Parent application paragraph 6 describes that data units are operated on and guided by fundamental properties of the human brain. Parent application paragraph 8 describes that memory operations are designed to model different human brain traits. Paragraph 51 states that the storage mimics the human brain. Parent application paragraph 63 states that the memory is designed according to human brain features. Finally, parent application paragraph 99 and the associated Table 2 shows how features of claim limitations correspond to features of the human brain. See below: PNG media_image1.png 106 615 media_image1.png Greyscale PNG media_image2.png 404 632 media_image2.png Greyscale Thus, the limitations of the claim as they stand are clearly mental steps, as Applicant has repeatedly described through the specification that they are already performed in the brain. Applicant’s goal is to perform the steps that the human brain already does. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. The claim recites additional elements which fail to integrate the judicial exception into a practical application. Claim 1 includes a digital memory system and one or more processors, which are at best an example of generic computing elements. The “data units” and storage language are at best examples of “generally linking the use of a judicial exception to a particular technological environment or field of use” of computing memory (see MPEP 2106.05(h)). The processors and data units are both recited at a high-level of generality (i.e., as a generic processor performing a generic computer function of ranking information based on a determined amount of use) such that it amounts no more than mere instructions to apply the exception using a generic computer component. Accordingly, these additional elements do not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea. Claims 2-12 and 25-30, which depend from independent claim 1, introduce further mental steps, such as selecting values, extracting values, increasing and decreasing values, adjusting values, merging data, selecting a node, determining whether an extraction suitability metric meets a threshold, extracting metadata, and generating an updated graph. These processes are described in the specification as processes modeled based on the human mind. See, for example, parent application par. 161, “In the human brain, memories are merged, reorganized, compressed and pushed around with the passage of time. To capture this aspect, the memory system 100 in various embodiments is allowed to do similar routine tasks in the background.” Also see the above rejection of claim 1, which details the examples in the specification of a human selecting and adjusting values. Like parent claim 1, these claims fall within the “mental processes” grouping of abstract ideas. These claims also fail to integrate the judicial exception into a practical application. Claims 2-4 introduce “data elements.” These are further examples of generic computer elements recited at a high-level of granularity generally linking the use of a judicial exception to a particular technological environment or field of use of computing memory. These claims are directed towards an abstract idea and are not patent eligible. Claim 13 is rejected using similar logic as claim 1. Claims 14-23, which depend from independent claim 13, introduce further mental steps, such as selecting values, extracting values, increasing and decreasing values, adjusting values, and merging data. These processes are described in the specification as processes modeled based on the human mind. See, for example, parent application par. 161, “In the human brain, memories are merged, reorganized, compressed and pushed around with the passage of time. To capture this aspect, the memory system 100 in various embodiments is allowed to do similar routine tasks in the background.” Also see the above rejection of claim 1, which details the examples in the specification of a human selecting and adjusting values. Like parent claim 13, these claims fall within the “mental processes” grouping of abstract ideas. These claims also fail to integrate the judicial exception into a practical application. Claims 14 and 15 introduce “data elements.” These are further examples of generic computer elements recited at a high-level of granularity generally linking the use of a judicial exception to a particular technological environment or field of use of computing memory. These claims are directed towards an abstract idea and are not patent eligible. Claim 24 is rejected using similar logic as claim 1. Response to Arguments Applicant's arguments filed 06/25/2026 have been fully considered but they are not persuasive. On page 9 of the response, Applicant states: “The examiner’s analogy to ‘organizing a photo album’ oversimplifies the technical nature of the claimed digital memory system architecture. The claims do not merely recite the abstract concept of organizing data; rather, they recite a specific technical implementation involving hives, localities, cue banks, and an inter-data unit connectivity graph that dynamically adjusts based on memory operations over time to improve system performance.” This is not an oversimplification by the examiner, as Applicant, in their own words, has thoroughly detailed how a human admin/user perform these operations, as detailed in the rejection above. In fact, Applicant has mapped these features to functions of the human brain: PNG media_image1.png 106 615 media_image1.png Greyscale PNG media_image2.png 404 632 media_image2.png Greyscale It cannot be considered an oversimplification by examiner, when Applicant has made been clear that the functions of the claimed subject matter are analogous to functions performed by a human. Applicant continues, “Furthermore, Desjardins cautions that "[w]hen evaluating a claim as a whole, examiners should not dismiss additional elements as mere 'generic computer components' without considering whether such elements confer a technological improvement to a technical problem, especially as to improvements to computer components or the computer system. Here, the claimed elements-including the specific architecture of hives, localities, cue banks, and the dynamically adjusting inter-data unit connectivity graph-are not generic computer components but rather constitute a particular technical solution that confers the technological improvements disclosed in the specification.” This is a misrepresentation of the examiner’s rejection. The generic computer elements listed in the rejection are processors, digital memories and data elements. The hives, localities, cue banks, and the dynamically adjusting inter-data unit connectivity graph are part of the abstract idea, that Applicant has described as being able to be performed by a human. Further, while Applicant invokes Desjardins, Applicant does not equate features from Desjardins to the features of Applicant’s claimed invention. It is not at all clear to the examiner how Desjardins, which is directed towards improvements in a machine learning model is equivalent to Applicant’s claimed invention, which is directed to improving a computer memory. Finally, on pages 9-10, Applicant invokes the non-precedential Ollnova decision to argue that the examiner is oversimplifying the claims by locking at them generally and failing to account for specific requirements of the claims. Again, it cannot be considered an “oversimplification” when Applicant has been very detailed in describing how the claims can be performed by a human/in a human mind, as detailed above. Lastly, Applicant has not demonstrated how specific pieces of claims of Ollnova are pertinent to specific pieces of the claimed invention. On its face, it does not appear to be similar at all, as Applicant’s claimed invention is not directed towards networks or communication protocol whatsoever. Accordingly, the eligibility analysis in the rejection above is proper. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN DARE whose telephone number is (571)272-4069. The examiner can normally be reached M-F 9:00-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RYAN DARE/Examiner, Art Unit 2132 /HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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Prosecution Timeline

Jan 27, 2025
Application Filed
Mar 25, 2026
Non-Final Rejection mailed — §101
Jun 25, 2026
Response Filed
Sep 16, 2026
Final Rejection mailed — §101 (current)

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Prosecution Projections

3-4
Expected OA Rounds
76%
Grant Probability
84%
With Interview (+8.1%)
3y 6m (~1y 10m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 591 resolved cases by this examiner. Grant probability derived from career allowance rate.

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